Patents by Inventor Kevin R. Shea

Kevin R. Shea has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7964471
    Abstract: A method of forming a capacitor includes providing material having an opening therein over a node location on a substrate. A shield is provided within and across the opening, with a void being received within the opening above the shield and a void being received within the opening below the shield. The shield is etched through within the opening. After the etching, a first capacitor electrode is formed within the opening in electrical connection with the node location. A capacitor dielectric and a second capacitor electrode are formed operatively adjacent the first capacitor electrode.
    Type: Grant
    Filed: March 3, 2010
    Date of Patent: June 21, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Mark Kiehlbauch, Kevin R. Shea
  • Patent number: 7935602
    Abstract: The invention includes methods of forming isolation regions. An opening can be formed to extend into a semiconductor material, and an upper periphery of the opening can be protected with a liner while a lower periphery is unlined. The unlined portion can then be etched to form a widened region of the opening. Subsequently, the opening can be filled with insulative material to form an isolation region. Transistor devices can then be formed on opposing sides of the isolation region, and electrically isolated from one another with the isolation region. The invention also includes semiconductor constructions containing an electrically insulative isolation structure extending into a semiconductor material, with the structure having a bulbous bottom region and a stem region extending upwardly from the bottom region to a surface of the semiconductor material.
    Type: Grant
    Filed: June 28, 2005
    Date of Patent: May 3, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Hongmei Wang, Fred D. Fishburn, Janos Fucsko, T. Earl Allen, Richard H. Lane, Robert J. Hanson, Kevin R. Shea
  • Publication number: 20100311219
    Abstract: A method of forming a plurality of capacitors includes an insulative material received over a capacitor array area and a circuitry area. The array area comprises a plurality of capacitor electrode openings within the insulative material received over individual capacitor storage node locations. The intervening area comprises a trench. Conductive metal nitride-comprising material is formed within the openings and against a sidewall portion of the trench to less than completely fill the trench. Inner sidewalls of the conductive material within the trench are annealed in a nitrogen-comprising atmosphere. The insulative material within the array area is etched with a liquid etching solution effective to expose outer sidewall portions of the conductive material within the array area. The conductive material within the array area is incorporated into a plurality of capacitors.
    Type: Application
    Filed: August 16, 2010
    Publication date: December 9, 2010
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Vishwanath Bhat, Kevin R. Shea
  • Patent number: 7824505
    Abstract: A method of removing a mask and addressing interfacial carbon chemisorbed in a semiconductor wafer starts with placing the semiconductor wafer into a dry strip chamber. The dry stripping process is performed to remove the mask on the semiconductor wafer. The semiconductor wafer is then subjected to a cleaning solution to perform a cleaning process to remove particles on the surface of the semiconductor wafer and to address the interfacial carbon. The cleaning solution being either water containing ozone (O3) and ammonia (NH3), or a solution of hot phosphoric acid (H3PO4).
    Type: Grant
    Filed: July 26, 2006
    Date of Patent: November 2, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Niraj Rana, Kevin R. Shea
  • Patent number: 7806988
    Abstract: A method of removing a mask and addressing interfacial carbon chemisbored in a semiconductor wafer starts with placing the semiconductor wafer into a dry strip chamber. The dry stripping process is performed to remove the mask on the semiconductor wafer. The semiconductor wafer is then subjected to a cleaning solution to perform a cleaning process to remove particles on the surface of the semiconductor wafer and to address the interfacial carbon. The cleaning solution being either water containing ozone (O3) and ammonia (NH3), or a solution of hot phosphoric acid (H3PO4).
    Type: Grant
    Filed: September 28, 2004
    Date of Patent: October 5, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Niraj Rana, Kevin R. Shea
  • Publication number: 20100221916
    Abstract: The invention includes methods in which one or more components of a carboxylic acid having an aqueous acidic dissociation constant of at least 1×10?6 are utilized during the etch of oxide (such as silicon dioxide or doped silicon dioxide). Two or more carboxylic acids can be utilized. Exemplary carboxylic acids include trichloroacetic acid, maleic acid, and citric acid.
    Type: Application
    Filed: May 11, 2010
    Publication date: September 2, 2010
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Niraj B. Rana, Kevin R. Shea, Janos Fucsko
  • Patent number: 7785962
    Abstract: A method of forming a plurality of capacitors includes an insulative material received over a capacitor array area and a circuitry area. The array area comprises a plurality of capacitor electrode openings within the insulative material received over individual capacitor storage node locations. The intervening area comprises a trench. Conductive metal nitride-comprising material is formed within the openings and against a sidewall portion of the trench to less than completely fill the trench. Inner sidewalls of the conductive material within the trench are annealed in a nitrogen-comprising atmosphere. The insulative material within the array area is etched with a liquid etching solution effective to expose outer sidewall portions of the conductive material within the array area. The conductive material within the array area is incorporated into a plurality of capacitors.
    Type: Grant
    Filed: February 26, 2007
    Date of Patent: August 31, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Vishwanath Bhat, Kevin R. Shea
  • Publication number: 20100193853
    Abstract: Methods of forming semiconductor devices that include one or more container capacitors include anchoring an end of a conductive member to a surrounding lattice material using an anchor material, which may be a dielectric. The anchor material may extend over at least a portion of an end surface of the conductive member, at least a portion of the lattice material, and an interface between the conductive member and the lattice material. In some embodiments, the anchor material may be formed without significantly covering an inner sidewall surface of the conductive member. Furthermore, in some embodiments, a barrier material may be provided over at least a portion of the anchor material and over at least a portion of an inner sidewall surface of the conductive member. Novel semiconductor devices and structures are fabricated using such methods.
    Type: Application
    Filed: February 4, 2009
    Publication date: August 5, 2010
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Brett Busch, Kevin R. Shea, Thomas A. Figura
  • Publication number: 20100151653
    Abstract: A method of forming a plurality of capacitors includes an insulative material received over a capacitor array area and a circuitry area. The array area comprises a plurality of capacitor electrode openings within the insulative material received over individual capacitor storage node locations. The intervening area comprises a trench. Conductive material is formed within the openings and against a sidewall portion of the trench to less than completely fill the trench. Covering material is formed over an elevationally outer lateral interface of the conductive material within the trench and the insulative material of the circuitry area. The insulative material within the array area is etched with a liquid etching solution effective to expose outer sidewall portions of the conductive material within the array area and to expose the conductive material within the trench. The conductive material within the array area is incorporated into a plurality of capacitors.
    Type: Application
    Filed: February 22, 2010
    Publication date: June 17, 2010
    Applicant: Micron Technology, Inc.
    Inventors: Vishwanath Bhat, Kevin R. Shea, Farrell Good
  • Patent number: 7713885
    Abstract: The invention includes methods in which one or more components of a carboxylic acid having an aqueous acidic dissociation constant of at least 1×10?6 are utilized during the etch of oxide (such as silicon dioxide or doped silicon dioxide). Two or more carboxylic acids can be utilized. Exemplary carboxylic acids include trichloroacetic acid, maleic acid, and citric acid.
    Type: Grant
    Filed: May 11, 2005
    Date of Patent: May 11, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Niraj B. Rana, Kevin R. Shea, Janos Fucsko
  • Publication number: 20100105186
    Abstract: The invention includes methods for selectively etching insulative material supports relative to conductive material. The invention can include methods for selectively etching silicon nitride relative to metal nitride. The metal nitride can be in the form of containers over a semiconductor substrate, with such containers having upwardly-extending openings with lateral widths of less than or equal to about 4000 angstroms; and the silicon nitride can be in the form of a layer extending between the containers. The selective etching can comprise exposure of at least some of the silicon nitride and the containers to Cl2 to remove the exposed silicon nitride, while not removing at least the majority of the metal nitride from the containers. In subsequent processing, the containers can be incorporated into capacitors.
    Type: Application
    Filed: January 6, 2010
    Publication date: April 29, 2010
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Kevin R. Shea, Thomas M. Graettinger
  • Patent number: 7682924
    Abstract: A method of forming a plurality of capacitors includes an insulative material received over a capacitor array area and a circuitry area. The array area comprises a plurality of capacitor electrode openings within the insulative material received over individual capacitor storage node locations. The intervening area comprises a trench. Conductive material is formed within the openings and against a sidewall portion of the trench to less than completely fill the trench. Covering material is formed over an elevationally outer lateral interface of the conductive material within the trench and the insulative material of the circuitry area. The insulative material within the array area is etched with a liquid etching solution effective to expose outer sidewall portions of the conductive material within the array area and to expose the conductive material within the trench. The conductive material within the array area is incorporated into a plurality of capacitors.
    Type: Grant
    Filed: August 13, 2007
    Date of Patent: March 23, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Vishwanath Bhat, Kevin R. Shea, Farrell Good
  • Patent number: 7683022
    Abstract: Various methods for selectively etching metal-containing materials (such as, for example, metal nitrides, which can include, for example, titanium nitride) relative to one or more of silicon, silicon dioxide, silicon nitride, and doped silicon oxides in high aspect ratio structures with high etch rates. The etching can utilize hydrogen peroxide in combination with ozone, ammonium hydroxide, tetra-methyl ammonium hydroxide, hydrochloric acid and/or a persulfate. The invention can also utilize ozone in combination with hydrogen peroxide, and/or in combination with one or more of ammonium hydroxide, tetra-methyl ammonium hydroxide and a persulfate. The invention can also utilize ozone, hydrogen peroxide and HCl, with or without persulfate. The invention can also utilize hydrogen peroxide and a phosphate, either alone, or in combination with a persulfate.
    Type: Grant
    Filed: July 13, 2006
    Date of Patent: March 23, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Kevin R. Shea, Niraj B. Rana
  • Patent number: 7683020
    Abstract: Various methods for selectively etching metal-containing materials (such as, for example, metal nitrides, which can include, for example, titanium nitride) relative to one or more of silicon, silicon dioxide, silicon nitride, and doped silicon oxides in high aspect ratio structures with high etch rates. The etching can utilize hydrogen peroxide in combination with ozone, ammonium hydroxide, tetra-methyl ammonium hydroxide, hydrochloric acid and/or a persulfate. The invention can also utilize ozone in combination with hydrogen peroxide, and/or in combination with one or more of ammonium hydroxide, tetra-methyl ammonium hydroxide and a persulfate. The invention can also utilize ozone, hydrogen peroxide and HCl, with or without persulfate. The invention can also utilize hydrogen peroxide and a phosphate, either alone, or in combination with a persulfate.
    Type: Grant
    Filed: July 13, 2006
    Date of Patent: March 23, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Kevin R. Shea, Niraj B. Rana
  • Patent number: 7683021
    Abstract: Various methods for selectively etching metal-containing materials (such as, for example, metal nitrides, which can include, for example, titanium nitride) relative to one or more of silicon, silicon dioxide, silicon nitride, and doped silicon oxides in high aspect ratio structures with high etch rates. The etching can utilize hydrogen peroxide in combination with ozone, ammonium hydroxide, tetra-methyl ammonium hydroxide, hydrochloric acid and/or a persulfate. The invention can also utilize ozone in combination with hydrogen peroxide, and/or in combination with one or more of ammonium hydroxide, tetra-methyl ammonium hydroxide and a persulfate. The invention can also utilize ozone, hydrogen peroxide and HCl, with or without persulfate. The invention can also utilize hydrogen peroxide and a phosphate, either alone, or in combination with a persulfate.
    Type: Grant
    Filed: July 13, 2006
    Date of Patent: March 23, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Kevin R. Shea, Niraj B. Rana
  • Patent number: 7666797
    Abstract: The invention includes methods for selectively etching insulative material supports relative to conductive material. The invention can include methods for selectively etching silicon nitride relative to metal nitride. The metal nitride can be in the form of containers over a semiconductor substrate, with such containers having upwardly-extending openings with lateral widths of less than or equal to about 4000 angstroms; and the silicon nitride can be in the form of a layer extending between the containers. The selective etching can comprise exposure of at least some of the silicon nitride and the containers to Cl2 to remove the exposed silicon nitride, while not removing at least the majority of the metal nitride from the containers. In subsequent processing, the containers can be incorporated into capacitors.
    Type: Grant
    Filed: August 17, 2006
    Date of Patent: February 23, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Kevin R. Shea, Thomas M. Graettinger
  • Patent number: 7667258
    Abstract: Double-sided container capacitors are formed using sacrificial layers. A sacrificial layer is formed within a recess in a structural layer. A lower electrode is formed within the recess. The sacrificial layer is removed to create a space to allow access to the sides of the structural layer. The structural layer is removed, creating an isolated lower electrode. The lower electrode can be covered with a capacitor dielectric and upper electrode to form a double-sided container capacitor.
    Type: Grant
    Filed: January 19, 2007
    Date of Patent: February 23, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, Kevin R. Shea, Chris W. Hill, Kevin J. Torek
  • Publication number: 20100041204
    Abstract: Some embodiments include methods of making stud-type capacitors utilizing carbon-containing support material. Openings may be formed through the carbon-containing support material to electrical nodes, and subsequently conductive material may be grown within the openings. The carbon-containing support material may then be removed, and the conductive material utilized as stud-type storage nodes of stud-type capacitors. The stud-type capacitors may be incorporated into DRAM, and the DRAM may be utilized in electronic systems.
    Type: Application
    Filed: August 13, 2008
    Publication date: February 18, 2010
    Inventors: Mark Kiehlbauch, Kevin R. Shea
  • Patent number: 7642196
    Abstract: Various methods for selectively etching metal-containing materials (such as, for example, metal nitrides, which can include, for example, titanium nitride) relative to one or more of silicon, silicon dioxide, silicon nitride, and doped silicon oxides in high aspect ratio structures with high etch rates. The etching can utilize hydrogen peroxide in combination with ozone, ammonium hydroxide, tetra-methyl ammonium hydroxide, hydrochloric acid and/or a persulfate. The invention can also utilize ozone in combination with hydrogen peroxide, and/or in combination with one or more of ammonium hydroxide, tetra-methyl ammonium hydroxide and a persulfate. The invention can also utilize ozone, hydrogen peroxide and HCl, with or without persulfate. The invention can also utilize hydrogen peroxide and a phosphate, either alone, or in combination with a persulfate.
    Type: Grant
    Filed: April 4, 2006
    Date of Patent: January 5, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Kevin R. Shea, Niraj B. Rana
  • Publication number: 20090047769
    Abstract: A method of forming a plurality of capacitors includes an insulative material received over a capacitor array area and a circuitry area. The array area comprises a plurality of capacitor electrode openings within the insulative material received over individual capacitor storage node locations. The intervening area comprises a trench. Conductive material is formed within the openings and against a sidewall portion of the trench to less than completely fill the trench. Covering material is formed over an elevationally outer lateral interface of the conductive material within the trench and the insulative material of the circuitry area. The insulative material within the array area is etched with a liquid etching solution effective to expose outer sidewall portions of the conductive material within the array area and to expose the conductive material within the trench. The conductive material within the array area is incorporated into a plurality of capacitors.
    Type: Application
    Filed: August 13, 2007
    Publication date: February 19, 2009
    Inventors: Vishwanath Bhat, Kevin R. Shea, Farrell Good