Patents by Inventor Kevin R. Shea
Kevin R. Shea has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7964471Abstract: A method of forming a capacitor includes providing material having an opening therein over a node location on a substrate. A shield is provided within and across the opening, with a void being received within the opening above the shield and a void being received within the opening below the shield. The shield is etched through within the opening. After the etching, a first capacitor electrode is formed within the opening in electrical connection with the node location. A capacitor dielectric and a second capacitor electrode are formed operatively adjacent the first capacitor electrode.Type: GrantFiled: March 3, 2010Date of Patent: June 21, 2011Assignee: Micron Technology, Inc.Inventors: Mark Kiehlbauch, Kevin R. Shea
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Patent number: 7935602Abstract: The invention includes methods of forming isolation regions. An opening can be formed to extend into a semiconductor material, and an upper periphery of the opening can be protected with a liner while a lower periphery is unlined. The unlined portion can then be etched to form a widened region of the opening. Subsequently, the opening can be filled with insulative material to form an isolation region. Transistor devices can then be formed on opposing sides of the isolation region, and electrically isolated from one another with the isolation region. The invention also includes semiconductor constructions containing an electrically insulative isolation structure extending into a semiconductor material, with the structure having a bulbous bottom region and a stem region extending upwardly from the bottom region to a surface of the semiconductor material.Type: GrantFiled: June 28, 2005Date of Patent: May 3, 2011Assignee: Micron Technology, Inc.Inventors: Hongmei Wang, Fred D. Fishburn, Janos Fucsko, T. Earl Allen, Richard H. Lane, Robert J. Hanson, Kevin R. Shea
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Publication number: 20100311219Abstract: A method of forming a plurality of capacitors includes an insulative material received over a capacitor array area and a circuitry area. The array area comprises a plurality of capacitor electrode openings within the insulative material received over individual capacitor storage node locations. The intervening area comprises a trench. Conductive metal nitride-comprising material is formed within the openings and against a sidewall portion of the trench to less than completely fill the trench. Inner sidewalls of the conductive material within the trench are annealed in a nitrogen-comprising atmosphere. The insulative material within the array area is etched with a liquid etching solution effective to expose outer sidewall portions of the conductive material within the array area. The conductive material within the array area is incorporated into a plurality of capacitors.Type: ApplicationFiled: August 16, 2010Publication date: December 9, 2010Applicant: MICRON TECHNOLOGY, INC.Inventors: Vishwanath Bhat, Kevin R. Shea
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Patent number: 7824505Abstract: A method of removing a mask and addressing interfacial carbon chemisorbed in a semiconductor wafer starts with placing the semiconductor wafer into a dry strip chamber. The dry stripping process is performed to remove the mask on the semiconductor wafer. The semiconductor wafer is then subjected to a cleaning solution to perform a cleaning process to remove particles on the surface of the semiconductor wafer and to address the interfacial carbon. The cleaning solution being either water containing ozone (O3) and ammonia (NH3), or a solution of hot phosphoric acid (H3PO4).Type: GrantFiled: July 26, 2006Date of Patent: November 2, 2010Assignee: Micron Technology, Inc.Inventors: Niraj Rana, Kevin R. Shea
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Patent number: 7806988Abstract: A method of removing a mask and addressing interfacial carbon chemisbored in a semiconductor wafer starts with placing the semiconductor wafer into a dry strip chamber. The dry stripping process is performed to remove the mask on the semiconductor wafer. The semiconductor wafer is then subjected to a cleaning solution to perform a cleaning process to remove particles on the surface of the semiconductor wafer and to address the interfacial carbon. The cleaning solution being either water containing ozone (O3) and ammonia (NH3), or a solution of hot phosphoric acid (H3PO4).Type: GrantFiled: September 28, 2004Date of Patent: October 5, 2010Assignee: Micron Technology, Inc.Inventors: Niraj Rana, Kevin R. Shea
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Publication number: 20100221916Abstract: The invention includes methods in which one or more components of a carboxylic acid having an aqueous acidic dissociation constant of at least 1×10?6 are utilized during the etch of oxide (such as silicon dioxide or doped silicon dioxide). Two or more carboxylic acids can be utilized. Exemplary carboxylic acids include trichloroacetic acid, maleic acid, and citric acid.Type: ApplicationFiled: May 11, 2010Publication date: September 2, 2010Applicant: MICRON TECHNOLOGY, INC.Inventors: Niraj B. Rana, Kevin R. Shea, Janos Fucsko
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Patent number: 7785962Abstract: A method of forming a plurality of capacitors includes an insulative material received over a capacitor array area and a circuitry area. The array area comprises a plurality of capacitor electrode openings within the insulative material received over individual capacitor storage node locations. The intervening area comprises a trench. Conductive metal nitride-comprising material is formed within the openings and against a sidewall portion of the trench to less than completely fill the trench. Inner sidewalls of the conductive material within the trench are annealed in a nitrogen-comprising atmosphere. The insulative material within the array area is etched with a liquid etching solution effective to expose outer sidewall portions of the conductive material within the array area. The conductive material within the array area is incorporated into a plurality of capacitors.Type: GrantFiled: February 26, 2007Date of Patent: August 31, 2010Assignee: Micron Technology, Inc.Inventors: Vishwanath Bhat, Kevin R. Shea
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Publication number: 20100193853Abstract: Methods of forming semiconductor devices that include one or more container capacitors include anchoring an end of a conductive member to a surrounding lattice material using an anchor material, which may be a dielectric. The anchor material may extend over at least a portion of an end surface of the conductive member, at least a portion of the lattice material, and an interface between the conductive member and the lattice material. In some embodiments, the anchor material may be formed without significantly covering an inner sidewall surface of the conductive member. Furthermore, in some embodiments, a barrier material may be provided over at least a portion of the anchor material and over at least a portion of an inner sidewall surface of the conductive member. Novel semiconductor devices and structures are fabricated using such methods.Type: ApplicationFiled: February 4, 2009Publication date: August 5, 2010Applicant: MICRON TECHNOLOGY, INC.Inventors: Brett Busch, Kevin R. Shea, Thomas A. Figura
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Publication number: 20100151653Abstract: A method of forming a plurality of capacitors includes an insulative material received over a capacitor array area and a circuitry area. The array area comprises a plurality of capacitor electrode openings within the insulative material received over individual capacitor storage node locations. The intervening area comprises a trench. Conductive material is formed within the openings and against a sidewall portion of the trench to less than completely fill the trench. Covering material is formed over an elevationally outer lateral interface of the conductive material within the trench and the insulative material of the circuitry area. The insulative material within the array area is etched with a liquid etching solution effective to expose outer sidewall portions of the conductive material within the array area and to expose the conductive material within the trench. The conductive material within the array area is incorporated into a plurality of capacitors.Type: ApplicationFiled: February 22, 2010Publication date: June 17, 2010Applicant: Micron Technology, Inc.Inventors: Vishwanath Bhat, Kevin R. Shea, Farrell Good
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Patent number: 7713885Abstract: The invention includes methods in which one or more components of a carboxylic acid having an aqueous acidic dissociation constant of at least 1×10?6 are utilized during the etch of oxide (such as silicon dioxide or doped silicon dioxide). Two or more carboxylic acids can be utilized. Exemplary carboxylic acids include trichloroacetic acid, maleic acid, and citric acid.Type: GrantFiled: May 11, 2005Date of Patent: May 11, 2010Assignee: Micron Technology, Inc.Inventors: Niraj B. Rana, Kevin R. Shea, Janos Fucsko
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Publication number: 20100105186Abstract: The invention includes methods for selectively etching insulative material supports relative to conductive material. The invention can include methods for selectively etching silicon nitride relative to metal nitride. The metal nitride can be in the form of containers over a semiconductor substrate, with such containers having upwardly-extending openings with lateral widths of less than or equal to about 4000 angstroms; and the silicon nitride can be in the form of a layer extending between the containers. The selective etching can comprise exposure of at least some of the silicon nitride and the containers to Cl2 to remove the exposed silicon nitride, while not removing at least the majority of the metal nitride from the containers. In subsequent processing, the containers can be incorporated into capacitors.Type: ApplicationFiled: January 6, 2010Publication date: April 29, 2010Applicant: MICRON TECHNOLOGY, INC.Inventors: Kevin R. Shea, Thomas M. Graettinger
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Patent number: 7682924Abstract: A method of forming a plurality of capacitors includes an insulative material received over a capacitor array area and a circuitry area. The array area comprises a plurality of capacitor electrode openings within the insulative material received over individual capacitor storage node locations. The intervening area comprises a trench. Conductive material is formed within the openings and against a sidewall portion of the trench to less than completely fill the trench. Covering material is formed over an elevationally outer lateral interface of the conductive material within the trench and the insulative material of the circuitry area. The insulative material within the array area is etched with a liquid etching solution effective to expose outer sidewall portions of the conductive material within the array area and to expose the conductive material within the trench. The conductive material within the array area is incorporated into a plurality of capacitors.Type: GrantFiled: August 13, 2007Date of Patent: March 23, 2010Assignee: Micron Technology, Inc.Inventors: Vishwanath Bhat, Kevin R. Shea, Farrell Good
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Patent number: 7683022Abstract: Various methods for selectively etching metal-containing materials (such as, for example, metal nitrides, which can include, for example, titanium nitride) relative to one or more of silicon, silicon dioxide, silicon nitride, and doped silicon oxides in high aspect ratio structures with high etch rates. The etching can utilize hydrogen peroxide in combination with ozone, ammonium hydroxide, tetra-methyl ammonium hydroxide, hydrochloric acid and/or a persulfate. The invention can also utilize ozone in combination with hydrogen peroxide, and/or in combination with one or more of ammonium hydroxide, tetra-methyl ammonium hydroxide and a persulfate. The invention can also utilize ozone, hydrogen peroxide and HCl, with or without persulfate. The invention can also utilize hydrogen peroxide and a phosphate, either alone, or in combination with a persulfate.Type: GrantFiled: July 13, 2006Date of Patent: March 23, 2010Assignee: Micron Technology, Inc.Inventors: Kevin R. Shea, Niraj B. Rana
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Patent number: 7683020Abstract: Various methods for selectively etching metal-containing materials (such as, for example, metal nitrides, which can include, for example, titanium nitride) relative to one or more of silicon, silicon dioxide, silicon nitride, and doped silicon oxides in high aspect ratio structures with high etch rates. The etching can utilize hydrogen peroxide in combination with ozone, ammonium hydroxide, tetra-methyl ammonium hydroxide, hydrochloric acid and/or a persulfate. The invention can also utilize ozone in combination with hydrogen peroxide, and/or in combination with one or more of ammonium hydroxide, tetra-methyl ammonium hydroxide and a persulfate. The invention can also utilize ozone, hydrogen peroxide and HCl, with or without persulfate. The invention can also utilize hydrogen peroxide and a phosphate, either alone, or in combination with a persulfate.Type: GrantFiled: July 13, 2006Date of Patent: March 23, 2010Assignee: Micron Technology, Inc.Inventors: Kevin R. Shea, Niraj B. Rana
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Patent number: 7683021Abstract: Various methods for selectively etching metal-containing materials (such as, for example, metal nitrides, which can include, for example, titanium nitride) relative to one or more of silicon, silicon dioxide, silicon nitride, and doped silicon oxides in high aspect ratio structures with high etch rates. The etching can utilize hydrogen peroxide in combination with ozone, ammonium hydroxide, tetra-methyl ammonium hydroxide, hydrochloric acid and/or a persulfate. The invention can also utilize ozone in combination with hydrogen peroxide, and/or in combination with one or more of ammonium hydroxide, tetra-methyl ammonium hydroxide and a persulfate. The invention can also utilize ozone, hydrogen peroxide and HCl, with or without persulfate. The invention can also utilize hydrogen peroxide and a phosphate, either alone, or in combination with a persulfate.Type: GrantFiled: July 13, 2006Date of Patent: March 23, 2010Assignee: Micron Technology, Inc.Inventors: Kevin R. Shea, Niraj B. Rana
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Patent number: 7666797Abstract: The invention includes methods for selectively etching insulative material supports relative to conductive material. The invention can include methods for selectively etching silicon nitride relative to metal nitride. The metal nitride can be in the form of containers over a semiconductor substrate, with such containers having upwardly-extending openings with lateral widths of less than or equal to about 4000 angstroms; and the silicon nitride can be in the form of a layer extending between the containers. The selective etching can comprise exposure of at least some of the silicon nitride and the containers to Cl2 to remove the exposed silicon nitride, while not removing at least the majority of the metal nitride from the containers. In subsequent processing, the containers can be incorporated into capacitors.Type: GrantFiled: August 17, 2006Date of Patent: February 23, 2010Assignee: Micron Technology, Inc.Inventors: Kevin R. Shea, Thomas M. Graettinger
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Patent number: 7667258Abstract: Double-sided container capacitors are formed using sacrificial layers. A sacrificial layer is formed within a recess in a structural layer. A lower electrode is formed within the recess. The sacrificial layer is removed to create a space to allow access to the sides of the structural layer. The structural layer is removed, creating an isolated lower electrode. The lower electrode can be covered with a capacitor dielectric and upper electrode to form a double-sided container capacitor.Type: GrantFiled: January 19, 2007Date of Patent: February 23, 2010Assignee: Micron Technology, Inc.Inventors: Gurtej S. Sandhu, Kevin R. Shea, Chris W. Hill, Kevin J. Torek
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Publication number: 20100041204Abstract: Some embodiments include methods of making stud-type capacitors utilizing carbon-containing support material. Openings may be formed through the carbon-containing support material to electrical nodes, and subsequently conductive material may be grown within the openings. The carbon-containing support material may then be removed, and the conductive material utilized as stud-type storage nodes of stud-type capacitors. The stud-type capacitors may be incorporated into DRAM, and the DRAM may be utilized in electronic systems.Type: ApplicationFiled: August 13, 2008Publication date: February 18, 2010Inventors: Mark Kiehlbauch, Kevin R. Shea
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Patent number: 7642196Abstract: Various methods for selectively etching metal-containing materials (such as, for example, metal nitrides, which can include, for example, titanium nitride) relative to one or more of silicon, silicon dioxide, silicon nitride, and doped silicon oxides in high aspect ratio structures with high etch rates. The etching can utilize hydrogen peroxide in combination with ozone, ammonium hydroxide, tetra-methyl ammonium hydroxide, hydrochloric acid and/or a persulfate. The invention can also utilize ozone in combination with hydrogen peroxide, and/or in combination with one or more of ammonium hydroxide, tetra-methyl ammonium hydroxide and a persulfate. The invention can also utilize ozone, hydrogen peroxide and HCl, with or without persulfate. The invention can also utilize hydrogen peroxide and a phosphate, either alone, or in combination with a persulfate.Type: GrantFiled: April 4, 2006Date of Patent: January 5, 2010Assignee: Micron Technology, Inc.Inventors: Kevin R. Shea, Niraj B. Rana
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Publication number: 20090047769Abstract: A method of forming a plurality of capacitors includes an insulative material received over a capacitor array area and a circuitry area. The array area comprises a plurality of capacitor electrode openings within the insulative material received over individual capacitor storage node locations. The intervening area comprises a trench. Conductive material is formed within the openings and against a sidewall portion of the trench to less than completely fill the trench. Covering material is formed over an elevationally outer lateral interface of the conductive material within the trench and the insulative material of the circuitry area. The insulative material within the array area is etched with a liquid etching solution effective to expose outer sidewall portions of the conductive material within the array area and to expose the conductive material within the trench. The conductive material within the array area is incorporated into a plurality of capacitors.Type: ApplicationFiled: August 13, 2007Publication date: February 19, 2009Inventors: Vishwanath Bhat, Kevin R. Shea, Farrell Good