Abstract: A circuit that includes a Darlington transistor pair having an input transistor and an output transistor configured to generate an output signal at an output node in response to an input signal received through the input node is disclosed. The circuit has a resistor-inductor-capacitor (RLC) type frequency bias feedback network communicatively coupled between the output transistor and the input node for providing biasing to the Darlington transistor pair as well as for adjusting at least one characteristic of an amplified version of the input signal that passes through the input transistor and into the frequency bias network. The circuit further includes a feedback coupling network coupled between the output node and the input node for feeding back to the input node a portion of the amplified version of the input signal that passes through the input transistor.

Abstract: Methods for fabricating a field effect transistor having at least one structure configured to redistribute and/or reduce an electric field from gate finger ends are disclosed. The methods provide field effect transistors that each include a substrate, an active region disposed on the substrate, at least one source finger in contact with the active region, at least one drain finger in contact with the active region, and at least one gate finger in rectifying contact with the active region. One embodiment has at least one end of the at least one gate finger extending outside of the active region. At least one method includes etching at least one gate channel into the passivation layer with a predetermined slope that reduces electric fields at a gate edge. Other methods include steps for fabricating a sloped gate foot, a round end, and/or a chamfered end to further improve high voltage operation.

Abstract: A field effect transistor having at least one structure configured to redistribute and/or reduce an electric field from gate finger ends is disclosed. Embodiments of the field effect transistor include a substrate, an active region disposed on the substrate, at least one source finger in contact with the active region, at least one drain finger in contact with the active region, and at least one gate finger in rectifying contact with the active region. One embodiment has at least one end of the at least one gate finger extending outside of the active region. Another embodiment includes at least one source field plate integral with the at least one source finger. The at least one source field plate extends over the at least one gate finger that includes a portion outside of the active region. Either embodiment can also include a sloped gate foot to further improve high voltage operation.

Abstract: A circuit that includes a Darlington transistor pair having an input transistor and an output transistor configured to generate an output signal at an output node in response to an input signal received through the input node is disclosed. The circuit has a frequency bias feedback network communicatively coupled between the output transistor and the input node for providing biasing to the Darlington transistor pair as well as for adjusting a phase and amplitude of an amplified version of the input signal that passes through the input transistor and into the frequency bias network. The circuit further includes a feedback coupling network coupled between the output node and the input node for feeding back to the input node a portion of the amplified version of the input signal that passes through the input transistor.

Abstract: A circuit that includes a Darlington transistor pair having an input transistor and an output transistor configured to generate an output signal at an output node in response to an input signal received through the input node is disclosed. The circuit has a frequency bias feedback network communicatively coupled between the output transistor and the input node for providing biasing to the Darlington transistor pair as well as for adjusting a phase and amplitude of an amplified version of the input signal that passes through the input transistor and into the frequency bias network. The circuit further includes a feedback coupling network coupled between the output node and the input node for feeding back to the input node a portion of the amplified version of the input signal that passes through the input transistor.

Abstract: An apparatus comprising an amplifier and a coupling circuit. The amplifier may be configured to generate an amplified output signal in response to a first input signal and a second input signal. The coupling circuit may be configured to generate the second input signal in response to the first input signal. The coupling circuit may be configured to increase a speed of propagation of the first input signal.

Abstract: A Darlington amplifier comprising a first stage and a second stage. The first stage generally comprises one or more first transistors and configured to generate a first and a second signal in response to an input signal. The second stage generally comprises one or more second transistors and may be configured to generate an output signal in response to the first and second signals. The Darlington amplifier may be configured to provide thermal emitter ballasting of the first transistors.

Abstract: An apparatus comprising an amplifier circuit and a control circuit. The amplifier circuit may be configured to generate an amplified signal in response to an input signal. The control circuit generally comprises a differential amplifier having (i) a first input coupled to said amplified signal and (ii) a second input coupled to a reference voltage. The control circuit may be configured to control a dynamic range of the amplifier circuit by adjusting the input signal based on (i) a loop gain of the control circuit and (ii) the reference voltage.

Abstract: An apparatus comprising a first amplifier, a second amplifier and a control circuit. The first amplifier may be configured to present a first amplified output signal in response to an input signal. The second amplifier may be configured to present a second amplified output signal to provide a shaped signal peaking response in response to the input signal. The first and second amplified output signals are generally combined. The control circuit may be configured to control a ratio between the first amplified output signal and the second amplified output signal. The ratio controls an amount of the peaking response.

Abstract: An apparatus comprising an amplifier circuit and a control circuit. The amplifier circuit may be configured to generate an amplified signal in response to an input signal. The control circuit generally comprises a differential amplifier having (i) a first input coupled to said amplified signal and (ii) a second input coupled to a reference voltage. The control circuit may be configured to control a dynamic range of the amplifier circuit by adjusting the input signal based on (i) a loop gain of the control circuit and (ii) the reference voltage.

Abstract: An apparatus comprising an amplifier circuit and a control circuit. The amplifier circuit may be configured to generate an amplified signal in response to an input signal. The control circuit generally comprises a differential amplifier having (i) a first input coupled to said amplified signal and (ii) a second input coupled to a reference voltage. The control circuit may be configured to control a gain of the amplifier circuit by adjusting the input signal based on (i) a magnitude of the amplified signal and (ii) the reference voltage.

Abstract: An apparatus comprising a modulator circuit, a first and a second control circuit. The modulator circuit may be configured to generate a modulated differential output signal in response to a differential input signal. The first control circuit may be configured to control a first predistortion of the differential input signal in response to a first portion of the differential output signal. The second control circuit may be configured to control a second predistortion of the differential input signal in response to a second portion of the differential output signal.

Abstract: 4-terminal HEMT-HBT composite devices, based upon monolithically integrated HEMT-HBT technology and configured in various topologies, are useful in a wide range of applications which currently utilize discrete MMICs. In particular, the 4-terminal topologies are easily configured as 3-terminal composite devices useful in various 2-port and 3-port MMIC circuit applications, such as low noise-high linearity amplifiers as well as mixers, which provide the benefits of a reduction in size, as well as corresponding cost while providing better performance than utilizing either HEMT or HBT devices individually.