Abstract: Techniques and circuitry that support switching operations required to exchange data between memory arrays and external data pads are provided. In a write path, such switching operations may include latching in and assembling a number of bits sequentially received over a single data pad, reordering those bits based on a type of access mode (e.g., interleaved or sequential), and performing scrambling operations based on chip organization (e.g., ×4, ×8, or ×16) a bank location being accessed. Similar operations may be performed (in reverse order) in a read path, to assemble data to be read out of a device.

Abstract: A memory circuit comprises a memory and an internal column counter for a read sequence in a compression test mode of the memory. The memory comprises an array of memory cells. The internal column counter is configured to provide a first column address for generating a compression register of expected data to compare to data read from the array of memory cells in response to a first read command, latch a second column address in response to a second read command while the first read command is executing, and provide the second column address for generating the compression register of expected data to compare to data read from the array of memory cells in response to the second read command once execution of the first read command is completed.

Abstract: A method of controlling an internal address counter which provides a count used in accessing a storage cell array to provide increased flexibility in the performance of a test on the array, comprising, rendering a normal overflow condition of the counter modified, thereby enabling alteration of the count provided by the counter in accordance with the requirements of the test being performed on the array.