Abstract: A nonvolatile memory supports a standby state where the memory is ready to receive an access command to execute, and a deep power down state where the memory ignores all access commands. The memory can transition from the standby state to the deep power down state in response to a threshold amount of time in the standby state. Thus, the memory can enter the standby state after a command and then transition to the deep power down state after the threshold time.

Abstract: Three-dimensional (3D) NAND components formed with control circuitry split across two wafers can provide for more area for control circuitry for an array, enabling improved 3D NAND system performance. In one example, a 3D NAND component includes a first die including a three-dimensional (3D) NAND array and first complementary metal oxide semiconductor (CMOS) control circuitry to access the 3D NAND array, and a second die vertically stacked and bonded with the first die, the second die including second CMOS control circuitry to access the 3D NAND array of the first die.

Abstract: Apparatus and methods are disclosed, such as an apparatus that includes a string of charge storage devices associated with a pillar (e.g., of semiconductor material), a source gate device, and a source select device coupled between the source gate device and the string. Additional apparatus and methods are described.

Abstract: A memory structure includes a plurality of memory cells between a first and a second terminal and a pair of first conductors within a first tier, where individual ones of the first conductors are coupled to the first terminal of a first adjacent pair of memory cells in a first row orthogonal to the first conductors. The memory structure further includes a pair of second conductors within a second tier and parallel to the first conductors, where individual ones of the second conductors are coupled to the first terminal of a second adjacent pair of memory cells in a second row. The memory structure further includes a third conductor between the first and second tiers, and between each of the pair of the first conductors and the pair of the second conductors. The third conductor is coupled to second terminals of both the first and second adjacent pairs of memory cells.

Abstract: A method, memory device and system. The memory device includes an active memory array including memory cells and address lines, the address lines including bitlines (BLs) and wordlines (WLs), each of the memory cells connected between one of the BLs and one of the WLs; a dummy array including dummy address lines, the dummy address lines including dummy BLs and dummy WLs; at least one shorting structure extending across and in electrical contact with at least some of the dummy address lines to electrically short the at least some of the dummy address lines together; and at least one contact structure extending from the dummy array and electrically coupled to the at least some of the dummy address lines to connect the at least some of the dummy address lines to a predetermined voltage.

Abstract: Apparatus and methods are disclosed, such as an apparatus that includes a string of charge storage devices associated with a pillar (e.g., of semiconductor material), a source gate device, and a source select device coupled between the source gate device and the string. Additional apparatus and methods are described.

Abstract: A method, memory device and system. The memory device includes an active memory array including memory cells and address lines, the address lines including bitlines (BLs) and wordlines (WLs), each of the memory cells connected between one of the BLs and one of the WLs; a dummy array including dummy address lines, the dummy address lines including dummy BLs and dummy WLs; at least one shorting structure extending across and in electrical contact with at least some of the dummy address lines to electrically short the at least some of the dummy address lines together; and at least one contact structure extending from the dummy array and electrically coupled to the at least some of the dummy address lines to connect the at least some of the dummy address lines to a predetermined voltage.

Abstract: Apparatus and methods are disclosed, such as an apparatus that includes a string of charge storage devices associated with a pillar (e.g., of semiconductor material), a source gate device, and a source select device coupled between the source gate device and the string. Additional apparatus and methods are described.

Abstract: Memory devices might be configured to perform methods including reading a first page of memory cells and flag data wherein the flag data indicates whether a second page of memory cells adjacent to the first page is programmed, and determining from the flag data whether to re-read the first page of memory cells with an adjusted read voltage; performing a sense operation on memory cells coupled to first data lines of a first array of memory cells and memory cells coupled to data lines of a second array of memory cells, and determining a program indication of memory cells coupled to second data lines from the sense operation performed on the memory cells coupled to the data lines of the second array of memory cells; and/or programming memory cells coupled to first data lines in a first array of memory cells, and programming memory cells coupled to second data lines in the first array of memory cells while programming memory cells coupled to data lines in a second array of memory cells with flag data indicative o

Abstract: A nonvolatile memory supports a standby state where the memory is ready to receive an access command to execute, and a deep power down state where the memory ignores all access commands. The memory can transition from the standby state to the deep power down state in response to a threshold amount of time in the standby state. Thus, the memory can enter the standby state after a command and then transition to the deep power down state after the threshold time.

Abstract: An integrated circuit memory includes a logic circuitry bonded to a memory array. For example, the logic circuitry is formed separately from the memory array, and then the logic circuitry and the memory array are bonded. The logic circuitry facilitates operations of the memory array and includes complementary metal-oxide-semiconductor (CMOS) logic components, such as word line drivers, bit line drivers, sense amplifiers for the memory array. In an example, instead of being bonded to a single memory array, the logic circuitry is bonded to and shared by two memory arrays. For example, the logic circuitry is between two memory arrays. Due to the bonding process, a bonding interface layer is formed. Thus, in such an example, a first bonding interface layer is between the logic circuitry and a first memory array, and a second bonding interface layer is between the logic circuitry and a second memory array.

Abstract: An integrated circuit memory includes a logic circuitry bonded to a memory array. For example, the logic circuitry is formed separately from the memory array, and then the logic circuitry and the memory array are bonded. The logic circuitry facilitates operations of the memory array and includes complementary metal-oxide-semiconductor (CMOS) logic components, such as word line drivers, bit line drivers, sense amplifiers for the memory array. In an example, instead of being bonded to a single memory array, the logic circuitry is bonded to and shared by two memory arrays. For example, the logic circuitry is between two memory arrays. Due to the bonding process, a bonding interface layer is formed. Thus, in such an example, a first bonding interface layer is between the logic circuitry and a first memory array, and a second bonding interface layer is between the logic circuitry and a second memory array.

Abstract: Embodiments of the present disclosure are directed towards techniques to provide a memory device with reduced capacitance. In one embodiment, a memory array is formed in a die, and includes one or more pillars and a plurality of wordlines coupled with the one or more pillars. Adjacent wordlines of the plurality of wordlines are separated by respective dielectric layers, which may include components, to reduce capacitance of the plurality of wordlines. The components comprise air gaps or low-k dielectric material. Other embodiments may be described and/or claimed.

Abstract: A memory structure can include a conductive channel, a charge storage structure adjacent to the conductive channel, and a strain-inducing layer adjacent to the conductive channel on a side opposite the charge storage structure. The strain-inducing layer can have a higher coefficient of thermal expansion (CTE) than the conductive channel.

Abstract: Embodiments of the present disclosure are directed towards a memory device with vertical string drivers, in accordance with some embodiments. In one embodiment, the memory device includes a plurality of wordlines formed in a stack of multiple tiers. The device further includes a semiconductor layer disposed on top of the plurality of wordlines. The device further includes a plurality of string drivers disposed in the semiconductor layer substantially perpendicular to the tier stack of the plurality of wordlines. The semiconductor layer provides respective gate connections for the plurality of string drivers. In some embodiments, the semiconductor layer may be fabricated of polysilicon. Other embodiments may be described and/or claimed.

Abstract: Apparatus and methods are disclosed, such as an apparatus that includes a string of charge storage devices associated with a pillar (e.g., of semiconductor material), a source gate device, and a source select device coupled between the source gate device and the string. Additional apparatus and methods are described.

Abstract: Embodiments of the present disclosure are directed towards a memory device with a split staircase, in accordance with some embodiments. In one embodiment, the memory device includes one or more pillars disposed in a die, and a plurality of wordlines formed in a stack of multiple tiers and coupled with the one or more pillars. At least some of the wordlines are split across the tiers into at least first and second portions. Respective ends of at least some wordlines of at least one of the first or second portions, at a location of the split, are exposed to provide electrical coupling with other components of the device. Other embodiments may be described and/or claimed.

Abstract: A memory structure can include a conductive channel, a charge storage structure adjacent to the conductive channel, and a strain-inducing layer adjacent to the conductive channel on a side opposite the charge storage structure. The strain-inducing layer can have a higher coefficient of thermal expansion (CTE) than the conductive channel.

Abstract: Wafer-to-wafer bonding is used to form three-dimensional (3D) memory components such as 3D NAND flash memory with shared control circuitry on one die to access arrays on multiple dies. In one example, a non-volatile storage device includes a first die including a 3D array of non-volatile storage cells and CMOS (complementary metal oxide semiconductor) circuitry. A second die including a second 3D array of non-volatile storage cells is vertically stacked and bonded with the first die. At least a portion of the CMOS circuitry of the first die to access both the first 3D array of non-volatile storage cells of the first die and the second 3D array of non-volatile storage cells of the second die.

Abstract: The present disclosure relates to providing a wordline bridge between wordlines of adjacent tiles of memory cells to reduce the number wordline staircases in 3D memory arrays. An apparatus may include a memory array having memory cells. The memory array includes a first block of pages of the memory cells in a first tile and a second block of pages of the memory cells in a second tile. The apparatus may also include a polysilicon wordline bridge that couples first wordlines of the first block to second wordlines of the second block to couple the first tile to the second tile. The wordline bridge may be formed by applying a hard mask over the first tile, the second tile, and over a portion of polysilicon that connects the first tile to the second tile.