Patents by Inventor Kheng-Chong Tan
Kheng-Chong Tan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9996415Abstract: A data correcting method for a rewritable non-volatile memory module is provided. The method includes: if a first user data read from a first physical programming unit cannot be corrected by a corresponding first parity code, reading at least one group parity code of a first encoded group that the first physical programming unit belongs to into a buffer, sending the group parity code to a correcting circuit, and reading a user data from physical programming units belonging to the first encoded group into the buffer and sending the user data and the group parity code to the correcting circuit in batches to obtain a corrected first user data corresponding to the first user data.Type: GrantFiled: June 15, 2016Date of Patent: June 12, 2018Assignee: PHISON ELECTRONICS CORP.Inventors: Ming-Jen Liang, Kheng-Chong Tan
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Publication number: 20170300379Abstract: A data correcting method for a rewritable non-volatile memory module is provided. The method includes: if a first user data read from a first physical programming unit cannot be corrected by a corresponding first parity code, reading at least one group parity code of a first encoded group that the first physical programming unit belongs to into a buffer, sending the group parity code to a correcting circuit, and reading a user data from physical programming units belonging to the first encoded group into the buffer and sending the user data and the group parity code to the correcting circuit in batches to obtain a corrected first user data corresponding to the first user data.Type: ApplicationFiled: June 15, 2016Publication date: October 19, 2017Inventors: Ming-Jen Liang, Kheng-Chong Tan
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Patent number: 9652378Abstract: A writing method, a memory controller and a memory storage device are provided. The writing method includes steps of: configuring logical addresses to map to part of physical programming units in a storage area, wherein at least one of the physical programming units stores a valid data; transmitting a first write command for writing data having a first data length to at least one of the physical programming units; receiving a status signal; and selecting a spare physical erasing unit and copying the valid data having a second data length to the spare physical erasing unit, after transmitting the first write command and before receiving the status signal, wherein the first data length is not greater than the second data length. Therefore, it prevents a host system from waiting too long when writing data.Type: GrantFiled: July 25, 2013Date of Patent: May 16, 2017Assignee: PHISON ELECTRONICS CORP.Inventors: Kuo-Hwa Ho, Kheng-Chong Tan
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Patent number: 9201785Abstract: A data writing method for a rewritable non-volatile memory module is provided. The method includes receiving a write command and data corresponding to the write command from a host system and temporarily storing the data into a buffer memory, and the data includes a plurality of sub-data streams. The method still includes transmitting the sub-data streams into the rewritable non-volatile memory module, thereby writing the sub-data streams into at least one physical erasing unit of the rewritable non-volatile memory module. The method further includes generating parity information based on at least portion of the sub-data streams; storing the parity information into the buffer memory and deleting the data from the buffer memory. Accordingly, the method can effectively utilize the storage space of the buffer memory.Type: GrantFiled: August 5, 2013Date of Patent: December 1, 2015Assignee: PHISON ELECTRONICS CORP.Inventors: Kheng-Chong Tan, Ming-Jen Liang
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Patent number: 9122583Abstract: A data writing method for a memory storage device having physical unit unions is provided, wherein each of the physical unit unions includes upper physical units and lower physical units. The method includes partitioning the physical unit unions into a storage area including a data area and a spare area; configuring logical units for mapping to the physical unit unions of the data area; and receiving update data from a host system. The method also includes: selecting several physical unit unions from the spare area as buffer physical unit unions; writing the update data only to a part of each of the buffer physical unit unions; and moving the update data from buffer physical unit unions to the storage area by using a copy procedure. Therefore, the time of performing a write command can be shorten and the lifespan of the memory storage device can be prolonged effectively.Type: GrantFiled: July 1, 2012Date of Patent: September 1, 2015Assignee: PHISON ELECTRONICS CORP.Inventors: Kheng-Chong Tan, Lai-Hock Chua
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Publication number: 20150161042Abstract: A memory management method, a memory controlling circuit unit and a memory storage device are provided. The method includes: configuring a plurality of super physical erasing units, wherein each of the super physical erasing units includes at least two physical erasing units. A first super physical erasing unit includes a first physical erasing unit and a second physical erasing unit that belong to different operation units. The first physical erasing unit and the second physical erasing unit store different parts of first data. The physical erasing unit storing least valid data from each operation unit is selected for executing a garbage collection procedure. Accordingly, an efficiency of the garbage collection procedure is increased.Type: ApplicationFiled: January 22, 2014Publication date: June 11, 2015Applicant: PHISON ELECTRONICS CORP.Inventors: Ming-Jen Liang, Kheng-Chong Tan
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Patent number: 9043536Abstract: A method of recording mapping information for a rewritable non-volatile memory module is provided. The method includes configuring a plurality of logical addresses, establishing at least one logical address mapping table, and storing the at least one logical address mapping table into the rewritable non-volatile memory module. The method also includes receiving data to be stored into a plurality of continuous logical addresses from a host system, writing the data into a plurality of physical programming units, updating mapping relations between the continuous logical addresses and the physical programming units in a corresponding logical address mapping table loaded to a buffer memory, storing a continuous mapping table in the buffer memory, and recording a continuous mapping record corresponding to the continuous logical addresses in the continuous mapping table.Type: GrantFiled: May 17, 2013Date of Patent: May 26, 2015Assignee: PHISON ELECTRONICS CORP.Inventors: Kuo-Hwa Ho, Kheng-Chong Tan
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Patent number: 9009399Abstract: A flash memory storage system having a flash memory controller and a flash memory chip is provided. The flash memory controller configures a second physical unit of the flash memory chip as a midway cache physical unit corresponding to a first physical unit and temporarily stores first data corresponding to a first host write command and second data corresponding to a second host write command in the midway cache physical unit, wherein the first and second data corresponding to slow physical addresses of the first physical unit. Then, the flash memory controller synchronously copies the first and second data from the midway cache physical unit into the first physical unit, thereby shortening time for writing data into the flash memory chip.Type: GrantFiled: October 22, 2014Date of Patent: April 14, 2015Assignee: Phison Electronics Corp.Inventors: Lai-Hock Chua, Kheng-Chong Tan
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Publication number: 20150039820Abstract: A flash memory storage system having a flash memory controller and a flash memory chip is provided. The flash memory controller configures a second physical unit of the flash memory chip as a midway cache physical unit corresponding to a first physical unit and temporarily stores first data corresponding to a first host write command and second data corresponding to a second host write command in the midway cache physical unit, wherein the first and second data corresponding to slow physical addresses of the first physical unit. Then, the flash memory controller synchronously copies the first and second data from the midway cache physical unit into the first physical unit, thereby shortening time for writing data into the flash memory chip.Type: ApplicationFiled: October 22, 2014Publication date: February 5, 2015Inventors: Lai-Hock Chua, Kheng-Chong Tan
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Publication number: 20140372667Abstract: A data writing method for a rewritable non-volatile memory module is provided. The method includes receiving a write command and data corresponding to the write command from a host system and temporarily storing the data into a buffer memory, and the data includes a plurality of sub-data streams. The method still includes transmitting the sub-data streams into the rewritable non-volatile memory module, thereby writing the sub-data streams into at least one physical erasing unit of the rewritable non-volatile memory module. The method further includes generating parity information based on at least portion of the sub-data streams; storing the parity information into the buffer memory and deleting the data from the buffer memory. Accordingly, the method can effectively utilize the storage space of the buffer memory.Type: ApplicationFiled: August 5, 2013Publication date: December 18, 2014Applicant: PHISON ELECTRONICS CORP.Inventors: Kheng-Chong Tan, Ming-Jen Liang
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Patent number: 8904086Abstract: A flash memory storage system having a flash memory controller and a flash memory chip is provided. The flash memory controller configures a second physical unit of the flash memory chip as a midway cache physical unit corresponding to a first physical unit and temporarily stores first data corresponding to a first host write command and second data corresponding to a second host write command in the midway cache physical unit, wherein the first and second data corresponding to slow physical addresses of the first physical unit. Then, the flash memory controller synchronously copies the first and second data from the midway cache physical unit into the first physical unit, thereby shortening time for writing data into the flash memory chip.Type: GrantFiled: February 22, 2010Date of Patent: December 2, 2014Assignee: Phison Electronics Corp.Inventors: Lai-Hock Chua, Kheng-Chong Tan
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Publication number: 20140325119Abstract: A writing method, a memory controller and a memory storage device are provided. The writing method includes steps of: configuring logical addresses to map to part of physical programming units in a storage area, wherein at least one of the physical programming units stores a valid data; transmitting a first write command for writing data having a first data length to at least one of the physical programming units; receiving a status signal; and selecting a spare physical erasing unit and copying the valid data having a second data length to the spare physical erasing unit, after transmitting the first write command and before receiving the status signal, wherein the first data length is not greater than the second data length. Therefore, it prevents a host system from waiting too long when writing data.Type: ApplicationFiled: July 25, 2013Publication date: October 30, 2014Applicant: PHISON ELECTRONICS CORP.Inventors: Kuo-Hwa Ho, Kheng-Chong Tan
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Publication number: 20140289451Abstract: A method of recording mapping information for a rewritable non-volatile memory module is provided. The method includes configuring a plurality of logical addresses, establishing at least one logical address mapping table, and storing the at least one logical address mapping table into the rewritable non-volatile memory module. The method also includes receiving data to be stored into a plurality of continuous logical addresses from a host system, writing the data into a plurality of physical programming units, updating mapping relations between the continuous logical addresses and the physical programming units in a corresponding logical address mapping table loaded to a buffer memory, storing a continuous mapping table in the buffer memory, and recording a continuous mapping record corresponding to the continuous logical addresses in the continuous mapping table.Type: ApplicationFiled: May 17, 2013Publication date: September 25, 2014Applicant: PHISON ELECTRONICS CORP.Inventors: Kuo-Hwa Ho, Kheng-Chong Tan
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Patent number: 8694748Abstract: A data merging method for merging valid data of one logical block in a rewritable non-volatile memory module is provided. The method includes assigning a plurality of log physical blocks for the logical block. The method also includes performing a data arrangement operation and a data move operation with a partial synchronization manner to copy the valid data of the logical block into the lower physical pages of the log physical blocks from a first data physical block and at least one spare physical block while programming the valid data of the logical block into a second data physical block from the lower physical pages of the log physical blocks in units of each physical page group. The method further includes remapping the logical block to the second physical block. Accordingly, the method can effectively shorten the time of merging valid data and improving the reliability of data writing.Type: GrantFiled: May 24, 2012Date of Patent: April 8, 2014Assignee: Phison Electronics Corp.Inventors: Kiang-Giap Lau, Kheng-Chong Tan
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Publication number: 20140089566Abstract: A data storing method and a memory controller and a memory storage apparatus using the same are provided. The method includes logically grouping physical erase units into a data area and a spare area; selecting a physical erase unit form the spare area as a first data collecting unit; and selecting a physical erase unit from the spare area as a second data collecting unit. The method also includes writing data received from a host into the first data collecting unit. The method further includes performing a data arranging operation to move valid data in a third physical erase unit to the second data collecting unit and associating the third physical erase unit with the spare area. Accordingly, the method can effectively enhance the performance of the write operation.Type: ApplicationFiled: November 7, 2012Publication date: March 27, 2014Applicant: PHISON ELECTRONICS CORP.Inventors: Chao-Han Wu, Kim-Hon Wong, Kheng-Chong Tan
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Patent number: 8645613Abstract: A data writing method for a flash memory and a control circuit and a storage system using the same are provided. The data writing method includes determining whether the size of data to be stored by a host system is smaller than a predetermined value according to a write command received from the host system, when the size of the data is smaller than the predetermined value, the data is written into a corresponding buffer physical block or a corresponding spare buffer physical block. The data writing method further includes combining valid data belonging to the same logical block during the executions of several write commands. Accordingly, the response time during the execution of each write command is shortened, and the problem of timeout is avoided.Type: GrantFiled: September 4, 2009Date of Patent: February 4, 2014Assignee: Phison Electronics Corp.Inventor: Kheng-Chong Tan
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Patent number: 8589620Abstract: A data writing method for a rewritable non-volatile memory module is provided. The method includes receiving at least one update data, wherein the update data belongs to at least one logical page of a first logical block, and the first logical block is mapped to a first physical block. The method also includes when a physical page of a second physical block that is corresponding to the logical page already stores data, selecting a third physical block from a free area, writing the update data into the third physical block, serving the third physical block as the child physical block of the first physical block, and executing an erasing operation on the second physical block, wherein the second physical block is currently a child physical block of the first physical block. Thereby, the method can effectively reduce the number of operations for merging data and increase the data writing speed.Type: GrantFiled: April 1, 2011Date of Patent: November 19, 2013Assignee: Phison Electronics Corp.Inventors: Kheng-Chong Tan, Lai-Hock Chua
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Publication number: 20130254461Abstract: A data writing method for a memory storage device having physical unit unions is provided, wherein each of the physical unit unions includes upper physical units and lower physical units. The method includes partitioning the physical unit unions into a storage area including a data area and a spare area; configuring logical units for mapping to the physical unit unions of the data area; and receiving update data from a host system. The method also includes: selecting several physical unit unions from the spare area as buffer physical unit unions; writing the update data only to a part of each of the buffer physical unit unions; and moving the update data from buffer physical unit unions to the storage area by using a copy procedure. Therefore, the time of performing a write command can be shorten and the lifespan of the memory storage device can be prolonged effectively.Type: ApplicationFiled: July 1, 2012Publication date: September 26, 2013Applicant: PHISON ELECTRONICS CORP.Inventors: Kheng-Chong Tan, Lai-Hock Chua
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Patent number: 8510502Abstract: A data writing method, a memory controller using the method, and a memory storage apparatus using the method are provided. The method includes selecting a physical block as a reserved physical block for a plurality of updated physical blocks. The method also includes, when a host system is about to write updated data into a logical page belonging to a logical block and a physical page, which corresponds to the logical page, of a substitute physical block, which corresponds to an updated physical block mapped to the logical block, has stored data, independently assigning the reserved physical block to the updated physical block mapped to the logical block and writing the updated data into the reserved physical block. Accordingly, the method can complete data writing without performing a data merge operation, thereby shortening the time for performing a write command.Type: GrantFiled: December 14, 2011Date of Patent: August 13, 2013Assignee: Phison Electronics Corp.Inventors: Kheng-Chong Tan, Lai-Hock Chua
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Publication number: 20130159605Abstract: A data merging method for merging valid data of one logical block in a rewritable non-volatile memory module is provided. The method includes assigning a plurality of log physical blocks for the logical block. The method also includes performing a data arrangement operation and a data move operation with a partial synchronization manner to copy the valid data of the logical block into the lower physical pages of the log physical blocks from a first data physical block and at least one spare physical block while programming the valid data of the logical block into a second data physical block from the lower physical pages of the log physical blocks in units of each physical page group. The method further includes remapping the logical block to the second physical block. Accordingly, the method can effectively shorten the time of merging valid data and improving the reliability of data writing.Type: ApplicationFiled: May 24, 2012Publication date: June 20, 2013Applicant: PHISON ELECTRONICS CORP.Inventors: Kiang-Giap Lau, Kheng-Chong Tan