Abstract: Systems and methods related to serial communication devices are provided. An example integrated circuit (IC) device includes interface circuitry coupled to a two-wire serial communication bus having a serial clock (SCL) line and a serial data (SDA) bus line. The IC device further includes bus stuck recovery circuitry to monitor for a local SDA fault condition at the IC device based on a number of clock cycles during which an internal SDA signal (e.g., generated by the IC device) drives the SDA bus line to a first signal state, the clock cycles based on a clock signal received from the SCL line; and responsive to the local SDA fault condition, release the SDA bus line independent of the internal SDA signal, where the SDA bus line is in a second signal state different from the first signal state based on the release.

Abstract: Embodiments of the disclosure provide improved mismatch shaping for a digital to analog converter, the method including splitting an original input of a circuit into a plurality of time interleaved data streams; element rotation selection (ERS) logic to process the plurality of time interleaved data streams; and directing one of the plurality of time interleaved data streams to the ERS logic according to a decision of a data-weighted sigma-delta (SD) modulator. In other example implementations, the method can further include multiplexing one of the plurality of time interleaved data streams to be provided to a barrel shifter. In yet other examples, the method can include monitoring a difference between the plurality of time interleaved data streams as a basis for the directing such that a data sample rate for the digital to analog converter is reduced over a time interval.

Abstract: Sensor apparatus and methods for operating the same for measuring acceleration are disclosed. In some embodiments, circuitry inside a sensor digitizes a measured acceleration signal from an accelerometer into a digitized acceleration signal, which is processed by a digital equalization filter within the sensor to provide an equalized acceleration signal. The equalized acceleration signal may have a frequency response that is substantially flat over a frequency range that extends beyond the resonant frequency of a MEMs sensor within the accelerometer of the sensor.

Abstract: Sensor apparatus and methods for operating the same for measuring acceleration are disclosed. In some embodiments, circuitry inside a sensor digitizes a measured acceleration signal from an accelerometer into a digitized acceleration signal, which is processed by a digital equalization filter within the sensor to provide an equalized acceleration signal. The equalized acceleration signal may have a frequency response that is substantially flat over a frequency range that extends beyond the resonant frequency of a MEMs sensor within the accelerometer of the sensor.

Abstract: Active Noise Cancellation (ANC) systems and methods that reduce latency to improve performance. In certain embodiments the systems sample a noise signal using a sample period to create a stream of digital signal data that is representative of the noise signal. A data transport layer carries the digital signal data to a signal processor. The transport layer temporally organizes the digital signal data to place the digital signal data within an initial phase of a sample period. The remaining phase of the sample period is set to a duration that allows the signal processor to process the digital signal data carried in the initial phase and to output the processed data during the same sample period. In this way, the processing of data occurs within one sample period and the latency is reduced and predictable.

Abstract: Improved switching techniques for controlling three-level current steering DAC cells are disclosed. The techniques include decoupling two current sources, implemented as field-effect transistors (FETs), of a DAC cell both from their respective bias sources and from a load for converting a zero digital input, where the decoupling is performed in a certain order. The techniques also include coupling the current sources to their respective bias sources and to the load for converting a non-zero digital input, where the coupling is also performed in a certain order. The certain order of decoupling and coupling the bias sources and the load to the current sources of a DAC cell are based on the phenomenon of current memory in FETs. Utilizing current memory when operating a DAC cell may allow reducing power consumption while preserving the high performance properties of a three-level current steering DAC.

Abstract: Systems and methods disclosed herein provide for enhancing the low frequency (DC) gain of an operational amplifier with multiple correlated level shifting capacitors. In an embodiment, the operational amplifier is level shifted with a first correlated level shifting capacitor in a first phase and, then, is level shifted again with at least a second correlated level shifting capacitor in at least a second, non-overlapping, consecutive phase. In an embodiment, the multiple correlated level capacitors are controlled by a switching circuit network.

Abstract: Fault detection techniques for control of sensor systems. A sensor control integrated circuit (“IC”) may include a fault detection system for coupling to the sensor supply lines. The system may detect faults for each of the sensor supply lines. The fault detection system may level shift sensor supply line signals from a first voltage domain to a second voltage domain appropriate for the fault detection system of the controller IC. The fault detection system may level shift source potential voltages from the first voltage domain to the second voltage domain to detect predetermined fault types. The fault detection system may compare the second domain voltages from the sensor supply lines to voltages representing predetermined fault types and may generate fault status indicators based on the comparison.

Abstract: An apparatus comprises a digital to analog converter (DAC) circuit configured to receive a time-varying a digital input signal and convert the digital input signal to an analog output signal, an output amplifier circuit operatively coupled to the output of the DAC circuit, a peak detector circuit operatively coupled to the input the DAC and configured to produce a signal envelope of the digital input signal, and logic circuitry. The logic circuitry is operatively coupled to the peak detector circuit and is configured to detect when the signal envelope satisfies a specified threshold value; and to adjust a drive capability of an output amplifier circuit of the DAC circuit according to the signal envelope.

Abstract: A discrete-time (e.g., digital) filter can be used as an interpolation filter for processing an oversampled input signal, such as included as a portion of a sigma-delta digital-to-analog conversion circuit. An interpolation filter control circuit can be configured to adjust a filter order of the discrete-time interpolation filter at least in part in response to information indicative of an envelope signal magnitude. For example, higher-level input signals might be processed using an interpolation filter having a stop-band attenuation that is more stringently-specified (e.g., having greater attenuation) than a corresponding attenuation used for lower-level input signals. The filter order can be variable, such as varied in response to a detected envelope magnitude of the input signal to achieve power savings as compared to a filter having fixed parameters.

Abstract: Improved mechanisms for applying noise-shaped segmentation techniques in a multi-bit DAC are disclosed. Noise-shaped segmentation refers to constructing two or more noise-shaped signals whose sum equals the original digital input signal by splitting each word of the input signal into two or more sub-words and converting each sub-word by a respective sub-word DAC group. Disclosed mechanisms include determining a range of amplitudes of a portion of the input signal over a certain time period, and, when converting digital words of that portion to analog values, limiting the number of sub-word DAC groups which are used for the conversion only to a number that is necessary for generating an analog output corresponding to the portion being evaluated, which number is determined based on the tracked amplitudes and could be smaller than the total number of sub-word DAC groups. Placing unused sub-word DAC groups into a power saving mode reduces power consumption.

Abstract: Systems and methods disclosed herein provide for enhancing the low frequency (DC) gain of an operational amplifier with multiple correlated level shifting capacitors. In an embodiment, the operational amplifier is level shifted with a first correlated level shifting capacitor in a first phase and, then, is level shifted again with at least a second correlated level shifting capacitor in at least a second, non-overlapping, consecutive phase. In an embodiment, the multiple correlated level capacitors are controlled by a switching circuit network.

Abstract: The present invention relates in one aspect to a DC linear voltage regulator circuit for generating a regulated DC output voltage based on a DC input voltage. The DC linear voltage regulator circuit comprises a DMOS pass transistor comprising drain, gate, source and bulk terminals wherein the drain terminal is connected to a regulator output which is configured to supply the regulated DC output voltage and the source terminal is connected to a regulator input for receipt of the DC input voltage. The DC linear voltage regulator circuit comprises a switchable leakage prevention circuit, connected to the bulk terminal of the DMOS pass transistor, and configured to automatically detect and interrupt a flow of leakage current from the regulator output to the bulk terminal.

Abstract: A sigma-delta modulator circuit selectively removes a dither signal previously added to an input of a quantizer circuit from the quantizer circuit output when addition of the dither signal causes a digital state change in the quantizer circuit output. Various examples for enabling the selective removal of the dither signal are described. In one embodiment, a second quantizer circuit provides a non-dithered output signal for comparison, by a digital comparator, with the dithered output signal. In another embodiment, a single quantizer circuit provides the dithered and non-dithered output signals in turn, for comparison. A subtraction circuit may remove the dither signal as appropriate. Embodiments enable retention of the improved limit cycle tone reduction achievable via dithering while reducing the need for circuits with increased signal headroom, and associated design complexity and power dissipation.

Abstract: Embodiments of the disclosure provide improved mechanisms for applying DEM techniques to a DAC comprising a plurality of cells. Disclosed mechanisms include keeping track of the amplitude of input digital signal over a certain time period to determine a range of amplitudes of a portion of the input signal, and, when converting the digital values of that portion to analog values and applying a particular DEM technique, limiting the number of DAC cells on which a DEM technique is applied only to a number that is necessary for generating the analog output corresponding to the tracked portion, which number is determined based on the tracked amplitudes and could be smaller than the total number of DAC cells. In this manner, mismatch error may be reduced for smaller input signal amplitudes. Whenever possible, unused DAC cells may be put into a power saving mode, providing the advantage of reduced power consumption.

Abstract: A transducer amplification circuit may include a preamplifier circuit with a signal input receiving a transducer signal to provide an amplified transducer signal comprising audible frequency components and ultrasonic frequency components. The transducer amplification circuit may include a first sigma-delta modulator configured to sample and quantize the amplified transducer signal to generate a first digital transducer signal comprising a first quantization noise signal. The first sigma-delta modulator may include a first noise transfer function having a high pass response in at least a portion of an audible frequency range to push the quantization noise signal to ultrasonic frequencies. A second sigma-delta modulator is configured to sample and quantize the amplified transducer signal to generate a second digital transducer signal comprising a second quantization noise signal.

Abstract: The present invention relates in one aspect to a DC linear voltage regulator circuit for generating a regulated DC output voltage based on a DC input voltage. The DC linear voltage regulator circuit comprises a DMOS pass transistor comprising drain, gate, source and bulk terminals wherein the drain terminal is connected to a regulator output which is configured to supply the regulated DC output voltage and the source terminal is connected to a regulator input for receipt of the DC input voltage. The DC linear voltage regulator circuit comprises a switchable leakage prevention circuit, connected to the bulk terminal of the DMOS pass transistor, and configured to automatically detect and interrupt a flow of leakage current from the regulator output to the bulk terminal.

Abstract: Power consumption of analog-to-digital converters (ADCs) is one important requirement for automotive and consumer devices. One flavor of an ADC is a dual quantizer architecture for oversampling delta-sigma modulators. The dual quantizer delta-sigma modulator has a first quantizer for digitizing the output of the loop filter and a second quantizer for digitizing the input of the quantizer. However, the quantization noise of the second quantizer is a highly correlated signal and significantly degrades the spectrum of the delta-sigma modulator. To address this issue, an improvement to the dual quantizer architecture is made to cancel the quantization noise of the second quantizer that is digitizing the input. Furthermore, the improvement allows the second quantizer to run at a much slower sampling rate than the first quantizer. Advantageously, the improvement provides reduction in power consumption and the overall area of modulator.

Abstract: Embodiments of the present disclosure provide improved switching techniques for controlling three-level DAC cells employing a return-to-hold scheme. Disclosed techniques include switching a DAC cell off for at least the duration of a time period between two hold periods while a digital value of zero is being converted. Because the DAC cell is switched off between two hold periods, the current source drain voltage is not disturbed during the critical transient times when D flip-flop outputs change, which happens during the hold periods, in response to change of digital values to be converted. In this manner, power consumption may be reduced while preserving the high performance properties of a three-level return-to-hold DAC.

Abstract: The invention may provide a temperature sensor device that includes an analog temperature sensor to generate a first base-emitter voltage and a second base-emitter voltage, and an analog-to-digital converter (ADC) to sample at the voltages and generate corresponding digital values. The temperature sensor device may also include a logic unit to calculate a digital temperature code from the digital values using a digital virtual reference.