Abstract: Active Noise Cancellation (ANC) systems and methods that reduce latency to improve performance. In certain embodiments the systems sample a noise signal using a sample period to create a stream of digital signal data that is representative of the noise signal. A data transport layer carries the digital signal data to a signal processor. The transport layer temporally organizes the digital signal data to place the digital signal data within an initial phase of a sample period. The remaining phase of the sample period is set to a duration that allows the signal processor to process the digital signal data carried in the initial phase and to output the processed data during the same sample period. In this way, the processing of data occurs within one sample period and the latency is reduced and predictable.

Abstract: A DC-to-DC converter includes an error integrator that further includes a first amplifier and a second amplifier that each includes a first input for receiving a reference voltage and a second input for receiving a feedback voltage, a capacitor to an output of the second amplifier, and a resistor including a first end being coupled to an output of the first amplifier and a second end being coupled to the capacitor.

Abstract: A transducer amplification circuit may include a preamplifier circuit with a signal input receiving a transducer signal to provide an amplified transducer signal comprising audible frequency components and ultrasonic frequency components. The transducer amplification circuit may include a first sigma-delta modulator configured to sample and quantize the amplified transducer signal to generate a first digital transducer signal comprising a first quantization noise signal. The first sigma-delta modulator may include a first noise transfer function having a high pass response in at least a portion of an audible frequency range to push the quantization noise signal to ultrasonic frequencies. A second sigma-delta modulator is configured to sample and quantize the amplified transducer signal to generate a second digital transducer signal comprising a second quantization noise signal.

Abstract: A DC-to-DC converter includes an error integrator that further includes a first amplifier and a second amplifier that each includes a first input for receiving a reference voltage and a second input for receiving a feedback voltage, a capacitor to an output of the second amplifier, and a resistor including a first end being coupled to an output of the first amplifier and a second end being coupled to the capacitor.

Abstract: A method and circuit to perform noise shaped splitting of a digital input signal may include using multiple layers to process the input signal. In the first layer, the most significant bits of the input signal may be distributed to a plurality of branches. Dynamic element matching may be performed using the least significant bits of the input signal. Based on the results of the dynamic element matching, values may be added to the plurality of branches. If there is insufficient data activity, dynamics enhancement may be performed to increase the data activity. The output signals of each of the plurality of branches in the first layer may be provided to a second layer, in which these steps can be repeated on each of the output signals. The outputs of the second layer may be provided to a plurality of three level unit elements.

Abstract: A digital audio interface may include two signal inputs to transmit audio data. A first signal line may carry digital serial audio data. The second signal line may carry a word clock signal to differentiate the serial audio data transmitted over the first signal line. In the case of stereo audio data, the word clock signal may correspond to a left-right clock signal and may differentiate audio data intended for a right channel from that intended for a left channel. The audio data may also be differentiated differently depending on the configuration, such as in the case that the transmitted audio data include audio for more than two channels. The word clock signal may be scaled to regenerate a bit clock signal used to encode the serial audio data over the first signal line. The encoding bit clock signal need not be transmitted.

Abstract: A method and circuit to perform noise shaped splitting of a digital input signal may include using multiple layers to process the input signal. In the first layer, the most significant bits of the input signal may be distributed to a plurality of branches. Dynamic element matching may be performed using the least significant bits of the input signal. Based on the results of the dynamic element matching, values may be added to the plurality of branches. If there is insufficient data activity, dynamics enhancement may be performed to increase the data activity. The output signals of each of the plurality of branches in the first layer may be provided to a second layer, in which these steps can be repeated on each of the output signals. The outputs of the second layer may be provided to a plurality of three level unit elements.

Abstract: The invention may provide a temperature sensor device that includes an analog temperature sensor to generate a first base-emitter voltage and a second base-emitter voltage, and an analog-to-digital converter (ADC) to sample at the voltages and generate corresponding digital values. The temperature sensor device may also include a logic unit to calculate a digital temperature code from the digital values using a digital virtual reference.

Abstract: Fault detection techniques for control of sensor systems. A sensor control integrated circuit (“IC”) may include a fault detection system for coupling to the sensor supply lines. The system may detect faults for each of the sensor supply lines. The fault detection system may level shift sensor supply line signals from a first voltage domain to a second voltage domain appropriate for the fault detection system of the controller IC. The fault detection system may level shift source potential voltages from the first voltage domain to the second voltage domain to detect predetermined fault types. The fault detection system may compare the second domain voltages from the sensor supply lines to voltages representing predetermined fault types and may generate fault status indicators based on the comparison.

Abstract: A digital PLL may be combined with an analog PLL so that the output of the digital PLL is at a frequency high enough to maintain stability in the analog PLL when an initial reference clock signal is too low to maintain stability in the analog PLL. The digital PLL may include a scaling circuit, such as a frequency divider in the feedback path of the PLL, to generate the higher frequency output signal from the lower frequency reference input signal. The digital PLL may also use an on-chip free run ring oscillator as the clock for the digital PLL engine.

Abstract: A voltage level shifter for a direct coupling of an external voltage source to a common mode of a circuit may include an amplifier, a voltage-controlled current source, a first and second resistors. A first input of the amplifier may be connected to the common mode. A second input of the amplifier may, via the first and second resistors, receive a voltage indicative of the external voltage source. The output of the amplifier may indicate a voltage difference between the first and second inputs. The voltage-controlled current source may be controlled by the voltage difference to supply a current to a common node of the first and second resistors so that the voltage difference between the first and second inputs may be minimized.

Abstract: A digital PLL may be combined with an analog PLL so that the output of the digital PLL is at a frequency high enough to maintain stability in the analog PLL when an initial reference clock signal is too low to maintain stability in the analog PLL. The digital PLL may include a scaling circuit, such as a frequency divider in the feedback path of the PLL, to generate the higher frequency output signal from the lower frequency reference input signal. The digital PLL may also use an on-chip free run ring oscillator as the clock for the digital PLL engine.

Abstract: A digital audio interface may include two signal inputs to transmit audio data. A first signal line may carry digital serial audio data. The second signal line may carry a word clock signal to differentiate the serial audio data transmitted over the first signal line. In the case of stereo audio data, the word clock signal may correspond to a left-right clock signal and may differentiate audio data intended for a right channel from that intended for a left channel. The audio data may also be differentiated differently depending on the configuration, such as in the case that the transmitted audio data include audio for more than two channels. The word clock signal may be scaled to regenerate a bit clock signal used to encode the serial audio data over the first signal line. The encoding bit clock signal need not be transmitted.

Abstract: A voltage level shifter for a direct coupling of an external voltage source to a common mode of a circuit may include an amplifier, a voltage-controlled current source, a first and second resistors. A first input of the amplifier may be connected to the common mode. A second input of the amplifier may, via the first and second resistors, receive a voltage indicative of the external voltage source. The output of the amplifier may indicate a voltage difference between the first and second inputs. The voltage-controlled current source may be controlled by the voltage difference to supply a current to a common node of the first and second resistors so that the voltage difference between the first and second inputs may be minimized.

Abstract: A system for converting digital signals into analog signals using sigma-delta modulation and includes a signed thermometer encoder for converting a plurality of signed binary data received at the encoder into a plurality of signed thermometer data and a rotational dynamic element matching (DEM) arrangement for receiving the plurality of signed binary data and the plurality of signed thermometer data. The rotational DEM arrangement further includes a first barrel shifter for receiving a positive thermometer data at a cycle, the first barrel shifter having a first pointer indicating a starting position of next positive thermometer data, and a second barrel shifter for receiving a negative thermometer data at a cycle, the second shifter having a second pointer indicating a starting position of next negative thermometer data, wherein the first pointer is circularly shifted as a function of positive binary data and the second pointer is circularly shifted as a function of negative binary data.

Abstract: A system for converting digital signals into analog signals using sigma-delta modulation and includes a signed thermometer encoder for converting a plurality of signed binary data received at the encoder into a plurality of signed thermometer data and a rotational dynamic element matching (DEM) arrangement for receiving the plurality of signed binary data and the plurality of signed thermometer data. The rotational DEM arrangement further includes a first barrel shifter for receiving a positive thermometer data at a cycle, the first barrel shifter having a first pointer indicating a starting position of next positive thermometer data, and a second barrel shifter for receiving a negative thermometer data at a cycle, the second shifter having a second pointer indicating a starting position of next negative thermometer data, wherein the first pointer is circularly shifted as a function of positive binary data and the second pointer is circularly shifted as a function of negative binary data.

Abstract: A system is disclosed for processing digital signals in a data converter. The system includes a thermometer encoder for receiving signed binary data and for providing signed thermometer data. The signed thermometer data includes positive thermometer data and negative thermometer data. The system also includes a shuffler that receives positive input data responsive to the positive thermometer data and receives negative input data responsive to the negative thermometer data. The system also includes a decoder for receiving output data from the shuffler and providing decoded data to an analog output stage.

Abstract: A dynamic frequency compensated operational amplifier having multiple gain settings includes a first differential to single ended amplifier stage; a second amplifier stage responsive to the first stage; a plurality of compensating capacitors; a multi-gain setting circuit for selectively setting the gain of the operational amplifier; and a control circuit, responsive to the gain set by the multi-gain setting circuit for connecting at least one of the compensating capacitors between the output and the input of the second amplifier stage for adjusting the frequency response of the operational amplifier.

Abstract: In an output stage for a DAC, such as an oversampled DAC, an apparatus and method which generates, for each bit clock period and for each bit to be converted, two or more (not just one) return-to-zero (RTZ) signals. The RTZ signals are delayed from the other (if two RTZ signals are employed, they are delayed by one-half clock cycle relative to each other). The two RTZ signals are summed to yield the DAC output from said bit.