Abstract: A semiconductor memory device generates an internal voltage by using one detecting circuit at the burn-in and normal modes. The semiconductor memory device includes a burn-in adjusting circuit to produce a burn-in mode test signal, a first reference voltage generating circuit to produce a first reference voltage for a burn-in test in response to the burn-in mode test signal, a second reference voltage generating circuit to produce a second reference voltage for a normal mode, a detecting circuit for detecting voltage levels of the first and second reference voltages and outputting a detection signal and an internal voltage generating circuit for generating an internal voltage in response to the detection signal.

Abstract: A semiconductor memory device is provided which includes a voltage detecting unit configured to compare a target voltage level with a fed-back internal voltage to output a detection signal in a normal mode, a driving unit configured to selectively drive an internal voltage terminal to a first or second power supply voltage according to an operation mode in response to the detection signal, and an enable control unit configured to control the driving unit in response to a control signal corresponding to the operation mode.

Abstract: A reference voltage supplying circuit can include an internal reference voltage generating unit configured to generate an internal reference voltage, a pad configured to receive an external reference voltage, a switching unit selectively configured to supply the internal reference voltage or the external reference voltage to an internal voltage generator in a test mode.

Abstract: A semiconductor memory device is described that includes memory banks having memory cells and are laid out as a matrix on a semiconductor chip body. The semiconductor memory device includes a first pad group having first pads that are arranged in a line between two adjoining memory banks and a second pad group having second pads that are also arranged in a line between the two adjoining memory banks parallel to the first pad group. At least one third pad group is also formed interposed between the first and second pad groups having at least one third pad allowing for a reduction in size of the semiconductor memory device.

Abstract: A voltage generating unit of a semiconductor memory device makes it possible to reduce a peak current value when generating a high voltage. The voltage generating unit of the semiconductor memory device includes a detecting unit configured to detect a voltage level of a high voltage by comparing a reference voltage with a fed-back high voltage, an oscillating unit configured to generate a plurality of clock signals with different operation time points on the basis of an output signal of the detecting unit, and a plurality of pumping units configured to generate the high voltage according to pumping control signals based on the clock signals.

Abstract: A semiconductor memory device that includes a first high voltage oscillator configured to generate a first control pulse in response to a first enable signal, a level shifter configured to generate a high voltage control pulse by boosting a level of the first control pulse using a source high voltage, and a first high voltage generator configured to generate a high voltage by boosting an external power supply voltage in response to the high voltage control pulse.

Abstract: A first input unit, coupled to a repair checking node through a first fuse, is for inverting a logic level of the repair checking node in response to a first address. A second input unit, coupled to the repair checking node through a two or more second fuses, is for inverting a logic level of the repair checking node in response to a second address. The number of the second fuses corresponds to a delay time between a transfer path of the first address and a transfer path of the second address. A repair detecting signal generating unit is for generating a repair detecting signal in response to the logic level of the repair checking node. Other embodiments are also described.

Abstract: An internal voltage generator for a semiconductor memory device is provided. The internal voltage generator includes a first reference voltage generator for generating a first reference voltage, a second reference voltage generator for generating a second reference voltage, a core voltage generator for raising a core voltage based on the first reference voltage, and a core voltage discharger for discharging the core voltage depending on the second reference voltage.

Abstract: A semiconductor memory device is capable of reducing a test time by sharing input pins of addresses for the test, thereby reducing test costs also. The semiconductor memory device includes first and second address buffer units. The first address buffer unit is configured to transmit a plurality of normal addresses to an internal circuit and store one or more of the received normal addresses. The second address buffer unit is configured to transmit one or more external bank addresses to the internal circuit as internal bank addresses in a normal mode and transmit addresses stored in the first address buffer unit to the internal circuit as the internal bank addresses in a test mode.

Abstract: A semiconductor memory device is capable of measuring internal voltages via a shared pad to reduce a chip size. The semiconductor memory device includes a selector and a monitoring pad. The selector is configured to select one of a plurality of internal signals in response to a test signal and output the selected internal signal. The monitoring pad is configured to output an output signal of the selector to an outside of the semiconductor memory device.

Abstract: A semiconductor device includes: a first reference voltage generator for generating a first reference voltage; a first band gap circuit for dividing a voltage at a second reference voltage output node to produce a first and a second band gap voltages having a property relative to temperature variations; a first comparator for receiving the first reference voltage as a bias input and comparing the first band gap voltage with the second band gap voltage; and a first driver for pull-up driving the second reference voltage output node in response to an output signal of the first comparator.

Abstract: A semiconductor memory device includes a bit line sense amplifier for sensing and amplifying data applied on a bit line; a first driver for driving a pull-up voltage line of the bit line sense amplifier to a voltage applied on a normal driving voltage terminal; an overdriving signal generator for generating an overdriving signal defining an overdriving period in response to an active command; an overdriving control signal generator for receiving the overdriving signal to generate an overdriving control signal for selectively performing an overdriving operation according to a voltage level of an overdriving voltage; and a second driver for driving the normal driving voltage terminal to the overdriving voltage in response to the overdriving control signal.

Abstract: A semiconductor device in which a decoupling capacitor is formed by supplying different power levels to a guard ring device is disclosed. The semiconductor device includes a guard ring, having conductive rings, which surrounds a memory chip. The conductive rings are stacked in a multiplayer structure, and insulation layers are formed between the conductive rings. Voltages of different levels are applied to adjacent conductive rings.

Abstract: A write driver of a semiconductor memory device over drives a local input/output line at a write operation in order to transmit data provided in a global input/output line to a core area at a stable voltage level. Therefore the write driver charges a stable voltage level corresponding to data inputted at the write operation in a cell capacitor. The write driver includes a pull-up/pull-down driver for pull-up/pull-down driving a second data line depending on data loaded on a first data line, a pulse generation circuit for generating pull-up over driving pulses activated for a predetermined time period at the initial time of an interval that the second data line is pull-up driven, and an over driver for pull-up driving the second data line by an over driving voltage higher than a pull-up voltage of the pull-up/pull-down driver in response to the pull-up over driving pulses.

Abstract: A semiconductor memory device can stabilize a voltage level of a normal driving voltage terminal in a normal driving operation, which is performed after an overdriving operation, even when an overdriving voltage is unstable due to environmental factors of the semiconductor memory device in the overdriving operation. The semiconductor memory device includes a bit line sense amplifier for performing an amplification operation using a normal driving voltage or an overdriving voltage to sense and amplify data applied to bit lines, a normal driving voltage compensator configured to drive a normal driving voltage terminal according to a voltage level of the normal driving voltage terminal and target normal driving voltage levels, and a discharge enable signal generator configured to generate a discharge enable signal by adjusting an activation period of the discharge enable signal according to the overdriving voltage.

Abstract: A semiconductor memory device includes a bit line sense amplifier for sensing and amplifying data applied on a bit line; a first driver for driving a pull-up voltage line of the bit line sense amplifier to a voltage applied on a normal driving voltage terminal; an overdriving signal generator for generating an overdriving signal defining an overdriving period in response to an active command; an overdriving control signal generator for receiving the overdriving signal to generate an overdriving control signal for selectively performing an overdriving operation according to a voltage level of an overdriving voltage; and a second driver for driving the normal driving voltage terminal to the overdriving voltage in response to the overdriving control signal.

Abstract: The present invention relates to a semiconductor memory device for sensing voltages of bit lines in high speed. The semiconductor memory device for sensing voltages of bit lines in high speed includes: a first bit line pair to a fourth bit line pair each coupled to a different unit cell array; a bit line sense amplifying means coupled to the first bit line pair to the fourth bit line pair for amplifying data transmitted through the first bit line pair to the fourth bit line pair; and a switching block for connecting one of the first bit line pair to the fourth bit line pair with the bit line sense amplifying means in response to a control signal.

Abstract: A circuit for generating a voltage of a semiconductor memory apparatus includes a control unit that outputs a driving control signal in response to an enable signal and a burn-in signal, a first voltage generating unit that generates and outputs a first voltage in response to the enable signal, and a voltage maintaining unit that maintains the first voltage in response to the driving control signal.

Abstract: A voltage generating circuit of semiconductor integrated circuit includes: a voltage controller that detects the level of an external supply voltage and outputs a voltage control signal; a voltage supplier that outputs the external supply voltage or a first internal voltage in response to the voltage control signal; and a first reference voltage generator that is supplied with an output voltage of the voltage supplier and generates a first reference voltage.

Abstract: The present invention relates to a semiconductor memory device for sensing voltages of bit lines in high speed. The semiconductor memory device for sensing voltages of bit lines in high speed includes: a first bit line pair to a fourth bit line pair each coupled to a different unit cell array; a bit line sense amplifying means coupled to the first bit line pair to the fourth bit line pair for amplifying data transmitted through the first bit line pair to the fourth bit line pair; and a switching block for connecting one of the first bit line pair to the fourth bit line pair with the bit line sense amplifying means in response to a control signal.