Abstract: A semiconductor memory apparatus includes an active signal generation unit that generates a plurality of active signals having different enable timings in response to a refresh signal, a precharge signal generation unit that delays at least one of the active signals to generate at least one precharge signal for enabling at least two equalizer signals at the same time, and a sense amplifier driver control unit that generates the plurality of equalizer signals for controlling individual sense amplifier drivers in response to the plurality of active signals and the precharge signal.

Abstract: An over-driver control signal generating apparatus includes a pulse generating unit for generating a pulse signal having a pulse width corresponding to a desired over-driving interval in response to an over-driving signal; a supply voltage level detecting unit for detecting a voltage level of a supply voltage to generate a detecting signal; and a selecting unit for outputting the pulse signal as a bit line over-driver control signal in response to the detecting signal.

Abstract: A semiconductor memory apparatus includes: a driving controller that decodes bank activating signals to generate a plurality of driving control signals, activates some of the driving control signals, and outputs the activated driving signals; and a plurality of internal voltage generators each of which outputs an internal voltage in response to a reference voltage and the corresponding driving control signal and is disposed between two different banks among a plurality of banks.

Abstract: An internal voltage generator is used in a semiconductor device. The generator includes a core voltage end, a first reference voltage generator for generating a first reference voltage, a second reference voltage generator having a test/option processor for generating a second reference voltage having a voltage level higher than that of the first reference voltage and setting the second reference voltage to one of a plurality of voltage levels, a core voltage driving unit for driving a voltage at the core voltage end based on the first reference voltage, and a core voltage discharger for discharging the voltage at the core voltage end based on the second reference voltage.

Abstract: An internal voltage generating circuit includes: a voltage supplying unit configured to selectively supply an external power supply voltage or a pumping voltage having a voltage level higher than the external power supply voltage, and an internal voltage generating unit configured to use the voltage supplied from the voltage supplying unit as a supply voltage.

Abstract: A semiconductor memory device generates an internal voltage by using one detecting circuit at the burn-in and normal modes. The semiconductor memory device includes a burn-in adjusting circuit to produce a burn-in mode test signal, a first reference voltage generating circuit to produce a first reference voltage for a burn-in test in response to the burn-in mode test signal, a second reference voltage generating circuit to produce a second reference voltage for a normal mode, a detecting circuit for detecting voltage levels of the first and second reference voltages and outputting a detection signal and an internal voltage generating circuit for generating an internal voltage in response to the detection signal.

Abstract: A first input unit, coupled to a repair checking node through a first fuse, is for inverting a logic level of the repair checking node in response to a first address. A second input unit, coupled to the repair checking node through a two or more second fuses, is for inverting a logic level of the repair checking node in response to a second address. The number of the second fuses corresponds to a delay time between a transfer path of the first address and a transfer path of the second address. A repair detecting signal generating unit is for generating a repair detecting signal in response to the logic level of the repair checking node. Other embodiments are also described.

Abstract: An internal voltage generator includes a voltage comparator operating in response to an enable signal, comparing a reference voltage with a feedback voltage and outputting a comparison signal through a first node. A driving controller outputs a drive control signal in response to the comparison signal. An output driver outputs an internal voltage through a second node in response to the drive control signal. An initial operation stabilizer controls the driving controller for a certain period at which the enable signal is enabled to block an output of the drive control signal.

Abstract: An internal voltage generator for a semiconductor memory device is provided. The internal voltage generator includes a first reference voltage generator for generating a first reference voltage, a second reference voltage generator for generating a second reference voltage, a core voltage generator for raising a core voltage based on the first reference voltage, and a core voltage discharger for discharging the core voltage depending on the second reference voltage.

Abstract: A semiconductor memory device includes a bit line sense amplifier for sensing and amplifying data applied on a bit line; a first driver for driving a pull-up voltage line of the bit line sense amplifier to a voltage applied on a normal driving voltage terminal; an overdriving signal generator for generating an overdriving signal defining an overdriving period in response to an active command; an overdriving control signal generator for receiving the overdriving signal to generate an overdriving control signal for selectively performing an overdriving operation according to a voltage level of an overdriving voltage; and a second driver for driving the normal driving voltage terminal to the overdriving voltage in response to the overdriving control signal.

Abstract: A semiconductor memory device includes a bit line sense amplifying block that senses and amplifies bit line data. A first driving block drives a pull up power line of the bit line sense amplifying block using a voltage applied to a normal driving voltage terminal. A second driving block drives the normal driving voltage terminal using an over driving voltage. An over driving signal generation block generates an over driving signal that defines an over driving interval in response to an active command. An external power supply voltage level detection block detects a voltage level of the external power supply voltage. A selective output block selectively outputs the over driving signal in response to an output signal of the external power supply voltage level detection block, wherein an output signal of the selective output block controls the second driving block.

Abstract: Disclosed are a connecting method of a sense amplifier and a semiconductor memory device using the same. The semiconductor memory device comprises a memory cell array including a plurality of word lines connected respectively to a plurality of memory cell blocks, each of which is composed of a plurality of memory cells, in a row direction of the memory cells, and a plurality of pairs of bit lines connected respectively to the plurality of memory cell blocks in a column direction of the memory cells; and a plurality of sense amplifier arrays, each of which includes a plurality of sense amplifiers, each of which is connected to bit lines and complementary bit lines of the plurality of pairs of bit lines, for sensing a potential difference between the bit lines and the complementary bit lines.

Abstract: The present invention discloses a circuit for detecting a negative word line voltage including a detecting unit for detecting a negative word line voltage in a detection node by using a plurality of loads coupled in series between a power supply terminal and a negative word line voltage terminal, a test signal generating unit for generating a plurality of test signals for detecting variations of the negative word line voltage, and a control unit driven according to the test signals, for controlling a potential of the detection node by adjusting a number of the loads of the detecting unit. The circuit for detecting the negative word line voltage can detect a wanted level of negative word line voltage by using the plurality of test signals without modifying the circuit, to reduce a development period of DRAM semiconductor products.

Abstract: The present invention relates to a semiconductor memory device for sensing voltages of bit lines in high speed. The semiconductor memory device for sensing voltages of bit lines in high speed includes: a first bit line pair to a fourth bit line pair each coupled to a different unit cell array; a bit line sense amplifying means coupled to the first bit line pair to the fourth bit line pair for amplifying data transmitted through the first bit line pair to the fourth bit line pair; and a switching block for connecting one of the first bit line pair to the fourth bit line pair with the bit line sense amplifying means in response to a control signal.