Abstract: An electronic device for media file caching for conserving resources is described. The electronic device includes a processor and instructions stored in memory. The electronic device monitors requests for a media file, stores media file information and determines whether the media file should be stored locally based on the media file information. If it is determined that the media file should be stored, the electronic device saves the media file and presents the media file.

Abstract: An electronic device for using pause to manage resources is described. The electronic device includes a processor and instructions stored in memory. The electronic device monitors a pause duration and determines whether to perform a resource management operation based on the pause duration. The electronic device performs the resource management operation based on the pause duration.

Abstract: Present embodiments relate to resource management. More particularly, these embodiments relate to a system and method for adaptively monitoring a plurality of applications making use of a finite number of resources. The embodiments permit application developers to specify preferred operation guidelines without detailed knowledge of the requirements of the system designer or user.

Abstract: A receive device receives video data in the form of an encoded video bit stream. A video decoder of the receive device identifies a portion of the video data corresponding to a first scene and determines a complexity for this first scene and also determines a quality of service for the receive device. If the complexity of the first portion of video data is greater than a complexity threshold value or the quality of service is less than a quality of service threshold value, then the video decoder uses a hardware accelerator to decode the portion of video data. If, however, the complexity of the portion of video data is less than the complexity threshold value and the quality of service is greater than the quality of service threshold value, then the video decoder may use software decoding to decode the portion of video data.

Abstract: A system and method to manage processes of a mobile device based on available power resources is disclosed. In a particular embodiment, an apparatus is disclosed that includes an interface configured to receive a user selection of a scheduled program to be received at a mobile device. The apparatus also includes a battery threshold calculator configured to determine a battery charge threshold based on at least one of a duration of the scheduled program and a processing complexity of the scheduled program. The apparatus includes an alert generator configured to generate a battery alert notification prior to receiving the scheduled program in response to a determination that a battery charge of the mobile device at a starting time of the scheduled program does not satisfy the battery charge threshold.

Abstract: This describes power saving techniques for emissive displays. In one example, a method includes detecting a static mode in an emissive display, mapping input signals to adjusted signals for a plurality of emissive elements of the emissive display based on magnitudes of the input signals, and applying the adjusted signals to selectively dim output of the plurality of emissive elements, in response to detecting the static mode. The techniques may achieve effects in an emissive display that are similar or better than effects of a transmissive display when the backlight is dimmed.

Abstract: A system and method to interrupt a component of a mobile communication device based on a mute command and a monitored operating condition is disclosed. In another particular embodiment, the method includes receiving a mute command at a mobile communication device while the mobile communication device is performing audio content processing. The method also includes monitoring an operating condition of the mobile communication device in response to receiving the mute command. The method includes determining whether to interrupt a component used to perform the audio content processing based on the monitored operating condition.

Abstract: A hybrid analog/digital STB includes a tuner supplying respective analog and digital television signal processing paths. The analog processing path provides demodulated composite analog video and audio signals and the digital processing path provides demodulated component digital video and audio signals. The demodulated analog and video signals are combined in composite or component form to achieve various desirable effects in a highly flexible system architecture. OSD and display map normalization functions are also integrated within the system architecture.

Abstract: A combined condition access and transport demultiplexer circuit comprises a decryption device receiving a demodulated transport bitstream including a plurality of multiplexed conditional access (CA) and product (e.g. video, audio and data) packets, each CA packet being identified by a CA PID and each product packet by a respective product PID. A comparator is provided for comparing the PID of each received packet with a plurality of stored PID values representing the CA PID and selected product PID's. A routing manager is responsive to the comparator for routing received CA packets from the decryption device to a conditional access circuit which controls the decryption device and for routing received product packets to appropriate output ports for further processing.

Abstract: A digital conditional access module for a subscriber terminal comprises a decryption device including at least one PID register and an associated countdown register. The decryption device is enabled for decrypting received product packets having a PID matching a PID stored in the PID register so long as the associated countdown register is characterized by a non-zero value. Decryption of a product packet results in the countdown register being decremented by a selected factor, the countdown register being prevented from assuming a zero value by setting its contents to a selected value in response to a received conditional access packet containing a PID matching the PID stored in the PID register. The selected value to which the countdown register is set may also be contained within the received conditional access packet.

Abstract: Each of a plurality of terminals in a two-way communications system includes a series of counters establishing a plurality of time slots synchronized to a downstream reference parameter. Upstream transmissions are effected by each terminal in one or more of the time slots which are defined by a downloaded message as comprising either a reserved slot or a contention slot. The downloaded message, which may also establish terminal transmission power levels and retransmission backoff algorithms for contention time slots, is derived on the basis of the population of subscriber terminals and the usage of the upstream channel.

Abstract: A cable television upstream data transmission system provides a plurality of uniquely assignable time slots for use by subscriber terminals in upstream data transmission. The unique assignment of time slots provides guaranteed access for each subscriber terminal during its time slot. The width and number of time slots are controlled by a pair of programmable values which may be downloaded from the cable system headend to accommodate dynamic changes of the cable system. A transmission modulator used within the subscriber terminal produces an upstream transmission carrier having a frequency locked to a common network reference signal such as the system symbol clock. The frequency of the carrier signal produced by the transmission modulator is programmably controlled by a plurality of program values which are selected to provide frequency and phase lock of the modulator's carrier to the symbol clock network reference signal.

Abstract: A cable television upstream data transmission system provides a plurality of time slots synchronized to the downstream symbol clock for use by subscriber terminals in upstream data transmission. The width and number of time slots are controlled by a pair of downloadable values to accommodate dynamic changes of the cable system. A transmission modulator used within the subscriber terminal produces an upstream transmission carrier having a frequency locked to the symbol clock. The frequency of the carrier signal produced by the transmission modulator is programmably controlled by a plurality of program values which are selected to provide frequency and phase lock of the modulator's carrier to the symbol clock.

Abstract: Upstream transmissions in a two-way communications network are effected from subscriber terminals in upstream packets having one of a plurality of different separately acknowledgeable acknowledgment tags. Downstream acknowledgments of upstream messages are contained in CA packets multiplexed with product packets to form a transport bitstream. The transport bitstream is applied to a digital conditional access module (DCAM) in the terminal which is controlled by the conditional access data bits of the CA packets. The DCAM includes a status register for storing the acknowledgment bits of the CA packets, which bits are coupled by a microprocessor for controlling the upstream transmitter.

Abstract: A multisync horizontal drive generator for use in a television receiver or computer monitor display is operative in response to an applied horizontal scan synchronizing signal. A delay network couples the horizontal sync signal to a gated detector which compares the delayed horizontal sync signal to a differentiated horizontal scan flyback signal to produce an error signal. A gain adjustable error amplifier couples the error signal to a summing network which includes a nominal frequency input. A range control detects the frequency of the horizontal drive signal and applies a range control signal to the summing network. The combined signal inputs are coupled from the summing network to a signal controllable current source which drives a saw forming network to produce a horizontal scan signal.

Abstract: A synchronizing signal front end processor for video monitors includes a synchronizing signal subprocessor which responds to computer generated horizontal and vertical rate scan signals to provide alternative scan signal coupling in the event of interruption or abnormalities of the applied scan signals. The processor also includes horizontal and vertical synchronizing signal subprocessors which produce output signals indicative of the polarity and frequency of the applied selected scan synchronizing signals. In addition, the vertical and horizontal sync subprocessors provide respective sync out of range signals during sync interruption or abnormality which are utilized to stabilize the monitor display scanning process while switching to alternative scan synchronizing signal sources.

Abstract: A geometry correction waveform synthesizer includes a plurality of DC controlled multipliers each coupled to respective sources of complimentary geometry correction signals. The DC controlled multipliers are coupled to respective gain control voltage sources as well as null adjustment voltage sources to provide a variable amplitude and polarity correction signal output. The individual correction signal outputs of the DC controlled multipliers are combined to form a composite geometry correction signal which is applied to a gain control circuit. The individual gain control signals used by the DC controlled multipliers are added to form a combined gain control signal which is used to control the composite correction signal amplitude and maintain correction signal amplitude within a predetermined range. An overall gain control couples the composite geometry correction signal to the scan system.

Abstract: An RGB preamplifier for a video display includes respective multipliers independently operable for adjusting the contrast of input primary and secondary video signals. The contrast adjusted video signals are added to form a combined display signal, the combined signal being applied to the first inputs of primary and secondary comparators each of which is also supplied with a respective reference DC level. The primary and secondary video signals are alternately nulled at horizontal line rate by nulling the corresponding multipliers. The primary comparator samples the combined signal when the secondary signal is nulled for clamping the DC level of the primary signal in relation to the primary reference DC level and the secondary comparator samples the combined signal when the primary signal is nulled for clamping the DC level of the secondary signal in relation to the secondary reference DC level.

Abstract: An oscillator control system includes a phase-locked loop having a programmable frequency divider operative within the loop. A switch is further included within the phase-locked loop to permit the loop to be open or closed in response to an input signal. A counter accumulates oscillator clock signal counts between each successive rising edge portion of the applied sync signal. A pair of shift registers sequentially store successive clock signal counts for the current and previous sync signal intervals. The output counts are compared for consistency by producing a difference signal therebetween which is utilized to control the phase-locked loop switch and close it once the consistency of sync signal has been established. The output counts of the shift registers are combined and used to provide a scaling factor which sets the frequency division of the programmable frequency divider within the phase-locked loop and properly scales the oscillator frequency to the sync signal frequency.

Abstract: A method of operating a multi-standard noise immune sync pulse recovery system establishes a time window during which a sync pulse is expected. The count of a counter is stored when a sync pulse occurs as expected, the counter is reset and a sync output is generated. Successive sync pulses occurring as expected are verified by comparison with the stored counts. When a first predetermined number of successive sync pulses occur as expected, a state of periodicity is established for the signal. The window is progressively narrowed to optimize the system noise immunity responsive to a second predetermined number of sync pulses occurring as expected. Sync outputs are generated in the place of expected sync pulses that do not occur during the window when the system is in the state of periodicity. The state of periodicity is lost when a third predetermined number of sync pulses do not appear as expected and the window is progressively widened.