Abstract: A frequency synthesis tuner for a television receiver includes a voltage controlled oscillator (VCO) responsive to a phase locked loop (PLL) for generating a local oscillator signal which is used to convert a received RF television signal to an intermediate frequency signal. An automatic fine tuning (AFT) detector develops an AFT error signal representing the frequency deviation of the converted signal from 45.75 MHz. Fine tuning is effected by controlling the reference and channel index dividers of the PLL in a coordinated manner in response to the AFT error signal for initially rapidly adjusting the frequency of the local oscillator signal to minimize the deviation of the converted signal from 45.75 MHz and then subsequently by further adjusting the frequency of the local oscillator signal in successive steps of adaptively increasing resolution.

Abstract: A television receiver for displaying a 4.times.3 aspect ratio color video signal on a 16.times.9 aspect ratio surface where the digitized luma and chroma signals have a 4:2:2 or a 4:1:1 relationship of Y, R-Y and B-Y samples. A signal having an equal number of luma and chroma samples is developed by generating additional chroma samples by averaging chroma sample values over a group of two (or four for a 4:1:1 signal) successive real values. The luma and chroma samples are compressed by twenty-five percent to form a converted color signal for display. In one version this is accomplished by discarding pixels when writing into a line memory. In another version this is accomplished by reading the pixels out of a line memory at 4/3 the write clock frequency.

Abstract: A programmable circuit for sampling an IR signal is responsive to a clock signal and a plurality of programmable factors which establish the characteristics of the sampling pattern. The circuit provides successive groups of samples whose resolution, phase and periodicity are established by the programmable factors such that IR signals characterized by different formats may be conveniently accommodated by the same hardware.

Abstract: A drop-out correction circuit for use in a VCR includes a generator for developing a gating signal identifying selected horizontal lines of a video signal containing spatially non-correlated encoded data. A control signal developed in response to a drop-out detection signal and the gating signal is applied to a drop-out corrector for providing a drop-out corrected signal at an output terminal except during the occurrence of said selected lines. A noise cancellation circuit operative except during the selected horizontal lines may be coupled to the output of the drop-out corrector.

Abstract: A luminance signal transient improver and non-linear peaking arrangement processes a digital luminance signal by generating a first difference signal and a second difference signal and developing therefrom a threshold control signal, a high frequency peaking signal and a low frequency peaking signal. The high frequency peaking signal consists of the second difference signal as modified by a high pass filter and the threshold control signal consists of the second difference signal as modified by a threshold circuit. The first difference signal is passed through an absolute value circuit and a low frequency emphasis circuit and modified by the threshold control signal and added to the high frequency peaking signal. The combined result is subjected to non-linear filtering and added to the luminance signal to form a horizontally processed luminance signal.

Abstract: A video system includes a scan converter for developing a progressively scanned display of video lines from a two field interlaced line system. A spatial array of six pixels covering two successive video lines is developed and gradients are determined between diagonally opposed pairs of pixels and a vertically opposed pair of pixels in the array. The interpolated pixel is developed by averaging the two pixels in the smallest of the gradients. A non-orthogonal display is developed by using horizontally interpolated pixels in the array developed by averaging successive pairs of real pixels, which introduces an offset of one-half pixel duration to the interpolated pixels. An adaptive peaking and noise coring circuit is included. Another spatial array of three line of pixels, both real and interpolated, is developed and a horizontal, a vertical and two diagonal gradients between pairs of pixels in the array are calculated.

Abstract: A balanced A/D converter system for a video signal. A clamp reference, corresponding to synchronizing pulse magnitude, is developed. The output of an A/D converter is summed with the clamp reference to develop a first correction signal for offsetting the video signal to the synchronizing pulse back porch level at the input of the A/D converter. A peak video reference signal is developed and summed with the output of the A/D converter to develop a second correction signal for controlling the gain of a variable gain amplifier coupled to the input of the A/D converter. Offsetting the video signal to the back porch level and amplifying the video signal based upon its maximum level enables the full utilization of the total range of the A/D converter.

Abstract: A video system includes a scan converter for developing a progressively scanned display of video lines from a two field interlaced line system. A spatial array of six pixels covering two successive video lines is developed and gradients are determined between diagonally opposed pairs of pixels and a vertically opposed pair of pixels in the array. The interpolated pixel is developed by averaging the two pixels in the smallest of the gradients. A non-orthogonal display is developed by using horizontally interpolated pixels in the array developed by averaging successive pairs of real pixels, which introduces an offset of one-half pixel duration to the interpolated pixels. An adaptive peaking and noise coring circuit is included. Another spatial array of three line of pixels, both real and interpolated, is developed and a horizontal, a vertical and two diagonal gradients between pairs of pixels in the array are calculated.

Abstract: A pulse-width modulator accepts a 7 bit binary signal input which is gated to an adder circuit. The adder is also supplied with a constant binary 1 input and has an output that is coupled to an 8 bit delay circuit that has its output coupled back to another input of the adder. The delay circuit and adder act as a recursive filter that is reset when the gate circuit is opened every 128th count. The most significant bit in the output of the delay circuit is a direct measure of the corresponding pulse width of the binary signal and is coupled to an integrating circuit.

Abstract: A three dimensional luma/chroma separation system with vertical detail generation is disclosed. The disclosed separation system uses three multiplexers to provide continuous, optimal separation of luma and chroma according to one of three separation or combing techniques as well as to provide the appropriate vertical detail signal for each luma/chroma separation technique. The disclosed system further provides input/output capability with special case applications, such as Super VHS format equipment and signals. Operation of the multiple multiplexers is controlled by signals generated according to actual picture content.

Abstract: A system and method for motion detection in a composite video signal is disclosed. These dimensional (horizontal, vertical and time) analysis is performed on actual picture element content to monitor variations therein. Vector generation, approximation and analysis gives information on picture element content for intra-field, inter-frame and inter-field signal processing. Additionally, noise immunity through selection of a convergence zone for the disclosed vector analysis is also provided. Control signals for further video signal processing are likewise generated.

Abstract: A video system includes a scan converter for developing a progressively scanned display of video lines from a two field interlaced line system. A spatial array of six pixels convering two successive video lines is developed and gradients are determined between diagonally opposed pairs of pixels and a vertically opposed pair of pixels in the array. The interpolated pixel is developed by averaging the two pixels in the smallest of the gradients. A non-orthogonal display is developed by using horizontally interpolated pixels in the array developed by averaging successive pairs of real pixels, which introduces an offset of one-half pixel duration to the interpolated pixels. An adaptive peaking and noise coring circuit is included. Another spatial array of three line of pixels, both real and interpolated, is developed and a horizontal, a vertical and two diagonal gradients between pairs of pixels in the array are calculated.

Abstract: A switching interface couples a plurality of video and audio signals from different sources to a single pair of audio outputs and a video output via a plurality of switches. A three wire serial data bus supplies the interface, which includes a serial to parallel converter, an address decoder, a data decoder and a control decoder for developing and applying appropriate switching control signals. A plurality of programmable gain amplifiers are provided for controlling the gain characteristics of the output video signals.

Abstract: A scan arrangement supplies real line video pixel information to an input demultiplexer that samples the pixels at a frequency of 4fc (fc=color subcarrier) and sequentially writes the sampled information in a series of line memories at an H (horizontal frequency) rate. A plurality of output multiplexers read information from the line memories at a 2H rate and supply it to a video interpolator where interpolated lines are produced based upon immediately adjacent real lines. The video output is at a 2H rate and consists of alternate real and interpolated lines in two successive fields. A vertical detail enhancement circuit combines pixel data from each set of three successive lines (upper (u), lower (l) and middle (m) lines) in accordance with the formula 2m-(u+1), to develop a vertical detail component.

Abstract: A digital video signal black level expander in which the dynamic range of the video signal is the criterion for expansion. The digital video signal is compared pixel by pixel in maximum and minimum comparators and the maximum and minimum pixel values for each field are stored in latches. Integrators average the maximum and minimum pixel values over successive pairs of fields of the video signal. The integrated minimum pixel value is subtracted from the integrated maximum pixel value to determine the dynamic range of the pixels in the video signal. A tilt-point pixel value is established as a function of the dynamic range, above which no expansion is permitted. Digital video signals below the tilt point are expanded. Programmable constants are supplied to modify the dynamic range effect and the amount of expansion as desired. A low pass filter removes high frequencies prior to comparing pixel values.

Abstract: A digital chroma signal processor samples groups of three successive pixels and develops first and second difference signals therefrom. The first difference signals indicate changes in color and the second difference signal peaks those changes when combined with the original signal. A threshold detector determines when the changes are great enough to need peaking and operates a multiplexer that supplies a transient enhanced signal for a chroma signal above the threshold or a median signal for a chroma signal below the threshold. The median signal is developed for each sample group, along with minimum and maximum signals, by a criteria filter. A limiting coefficient adjusts the minimum and maximum signals to provide controlled amounts of overshoot and undershoot in the processed chroma signal.

Abstract: A digital auto tracking system compares sampled operating data from a CRT with corresponding reference data and develops an error signal therefrom. The error signal is truncated to produce a desensitized three bit error signal. Three AND gates each have one input supplied with the three error bits, respectively, and three programmable velocity control bits are supplied to the other inputs by a microprocessor. A demultiplexer has a plurality of input taps that are coupled together so as to provide a minimum of zero and a maximum of seven clock pulses depending upon the outputs of the AND gates. The clock pulses sequence up/down counters in accordance with the derived error signal. The speed or velocity of change in response to the error signal is determined by the velocity control bits which may be microprocessor controlled for optimum block and white tracking of the particular cathode ray tube.

Abstract: A digital television chassis and a picture-in-picture module are interconnected with control microprocessor means via a three wire communications bus. Function control units in the digital chassis and in the picture-in-picture module have identical digital addresses. A logic circuit is interposed in the Ident line from the microprocessor and the Ident lines to each of the digital chassis and PIP module for selectively controlling the digital chassis and the PIP module. The microprocessor addresses the logic circuit and provides a Data signal indicating which of the digital chassis and PIP module is to be controlled.

Abstract: A television receiver is arranged to selectively display images from several input signal sources--such as pix-in-pix, teletext, computer graphics, besides displaying pictures from the normal off-the-air television signal. In accordance with this invention, clamping circuits are provided for establishing a constant black image reference level for all the input signals.