Abstract: In one embodiment, a WCDMA FDD system includes an embedded filter that provides a complex load to transistors in a low noise amplifier. The complex load can be constructed using passive and/or active devices and creates an arbitrary transfer function that supports selective Q-enhancement of poles or zeros. One particular implementation of the embedded filter is in the form of an LC tank circuit. The LC tank circuit is operably coupled to the output of the low noise amplifier and creates a transfer function whose poles and zeros can be selected to reject transmitter leakage in the WCDMA system, while maintain a desirable gain at the frequency of operation.

Abstract: Systems and methods for measuring and compensating a DC-transfer characteristic of analog-to-digital converters are described. A test-signal generator comprising a sigma-delta modulator may provide calibration signals to an ADC. An output from the ADC may be filtered with a notch filter to suppress quantization noise at discrete frequencies introduced by the sigma-delta modulator. The resulting filtered signal may be compared against an input digital signal to the test-signal generator to determine a transfer characteristic of the ADC.

Abstract: A method and apparatus for a digitally-corrected analog-to-digital converter (ADC) are disclosed. The apparatus comprises a nonlinearity generator that generates one or more nonlinear characteristics of a time varying input signal and that causes unwanted signal components at frequencies other than a frequency of the time varying input signal, a frequency modifier coupled to the nonlinearity generator that modifies the unwanted signal components by altering an amplitude of the unwanted signal components, a frequency compensator coupled to the frequency modifier, wherein the frequency compensator compensates for the modification introduced by the frequency modifier to provide a filtered digital signal, and an inverse nonlinearity generator coupled to the frequency compensator for receiving the filtered digital signal, wherein the inverse nonlinearity generator compensates for the one or more nonlinear characteristics.

Abstract: A circuit includes a frequency generation circuit having a phase locked loop, PLL, arranged to generate a carrier frequency; and a controller operably coupled to the frequency generation circuit and arranged to determine a frequency location of one or more signals output by the frequency generation circuit and provide a control signal thereto to adjust the carrier frequency generated by the frequency generation circuit. The controller is arranged to: cooperate with the PLL to introduce a frequency offset in the generated carrier frequency in a first frequency direction; and introduce a compensating frequency offset in a baseband transmit signal in a second frequency direction opposite to the first frequency direction.

Abstract: A transmitter circuit includes a frequency generation circuit configured to generate a local oscillator signal and a digital modulator configured to: receive data to be transmitted; quadrature modulate the received data to at least a first, Q, modulated value and a second, I, modulated value; examine the quadrature modulated data to determine if the first, Q, modulated value exceeds a limit, and in response thereto selectively modify the quadrature modulated values to a first modified, Q?, modulated value and a second modified, I?, modulated value thereby bringing only a value of the first modified, Q?, modulated value to within the limit. A local oscillator phase is selected in order to map the first modified, Q?, modulated value and second modified, I?, modulated value to desired quadrature values. A digital power amplifier, DPA, coupled to the digital quadrature modulator, is configured to amplify the quadrature modified modulated data.

Abstract: A predistortion function is evaluated with in-phase (I) and quadrature (Q) data words as arguments, while additive I and Q data words are generated in accordance with a comparison of the I and Q data words with a full scale value that generates maximum current in a digital power amplifier. The additive I and Q data words are added to the computed I and Q data words to produce predistorted I and Q data words. The predistorted I and Q data words are provided in a sequence to the digital power amplifier, which generates a corresponding radio-frequency (RF) analog signal.

Abstract: To compensate for second-order intermodulation (IM2), it is determined whether a blocking signal is present at a receiver. A biasing differential is applied across downconverting mixers in the receiver that minimizes cross-correlation of quadrature signal components of a signal produced by the receiver in the presence of the blocking signal.

Abstract: A digital transmitter includes: a plurality of adjustable delay lines arranged to delay a plurality of digital input signals by a plurality of delay times to generate a plurality of delayed digital input signals respectively; a plurality of converting devices arranged to convert the plurality of delayed digital input signals into a plurality of converting signals respectively; and a calibration device arranged to adjust a delay time of at least one adjustable delay line in the plurality of adjustable delay lines to make the plurality of converting devices convert the plurality of delayed digital input signals at respective desire time points.

Abstract: A digital transmitter includes: a plurality of converting devices arranged to generate a plurality of converting signals according to a plurality of digital input signals; a compensation device arranged to generate at least one compensation signal according to the plurality of digital input signals; and a combining circuit arranged to output an amplified output signal according to the plurality of converting signals and the at least one compensation signal.

Abstract: A reconfigurable circuit block includes a rate-conversion circuit, a processing circuit, a first asynchronous interface circuit, and a second asynchronous interface circuit. The rate-conversion circuit converts a first input signal into a first output signal. The processing circuit processes a second input signal to generate a second output signal. The first asynchronous interface circuit outputs a third output signal asynchronous with the first output signal. The second asynchronous interface circuit outputs a fourth output signal asynchronous with the second output signal. The controllable interconnection circuit transmits the third output signal to the processing circuit to serve as the second input signal when controlled to have a first interconnection configuration, and transmits the fourth output signal to the rate-conversion circuit to serve as the first input signal when controlled to have a second interconnection configuration.

Abstract: Aspects of the disclosure provide a transmitter that includes a pre-distortion module and a phase controller. The pre-distortion module is configured to receive a first digital value and generate a first pre-distorted digital value based on the first digital value and a corresponding angle. The first digital value is a combination of an in-phase component and a quadrature component of a signal for transmission. The phase controller is configured to control an amplifier to drive a current according to the first pre-distorted digital value and phase information in relation to the first digital value during a first phase range of a carrier signal determined at least partially based on the angle.

Abstract: An electronic device includes an input configured to receive at least one baseband input signal and at least one mixer downstream from the input. The electronic device also includes a phase-locked loop (PLL) including a voltage controlled oscillator (VCO) and a phase detector coupled thereto, the VCO coupled to the at least one mixer. A power amplifier is downstream from the at least one mixer and generates at least one aggressing signal that would otherwise generate an output pull of the VCO. The electronic device also includes a VCO pulling compensation circuit coupled to the input and the VCO and configured to compensate the VCO for the output pull based upon the at least one baseband input signal and the at least one aggressing signal.

Abstract: A communication system including a configurable sample rate converter and a controller is provided. The configurable sample rate converter, configured to convert a digital signal with a first sample rate to a converted signal with a second sample rate, being operable in one of a first configuration and a second configuration. The controller, configured to dynamically control the sample rate converter to operate in one of the first configuration and the second configuration according to at least one condition.

Abstract: A transceiver and a method of controlling aberrant transceiver operation. In one embodiment, the transceiver includes: (1) a processor, (2) an interrupt system coupled to the processor and having a flag register associated therewith, (3) detection circuits associated with corresponding functional units of the transceiver and configured to detect conditions regarding the corresponding functional units and set corresponding flags in the flag register, the interrupt system configured to assert interrupts in response thereto and (4) an interrupt-handing routine executable in the processor and configured to respond to the interrupts by carrying out at least one of loading parameters and generating warnings based on identities of the flags.

Abstract: To compensate for second-order intermodulation (IM2), it is determined whether a blocking signal is present at a receiver. A biasing differential is applied across downconverting mixers in the receiver that minimizes cross-correlation of quadrature signal components of a signal produced by the receiver in the presence of the blocking signal.

Abstract: A baseband signal is generated as a sequence of complex sample values at a predetermined sample rate. A sample of the baseband signal is captured as is a sample of an output signal generated by a power amplifier from the captured sample of the baseband signal. Complex values are iteratively assigned to a complex factor intended for predistorting data such that the product of the baseband signal sample and the complex factor converges towards equivalence with the output signal sample with each iterative assignment of the complex values to the complex factor. The complex factor is stored in memory at an address associated with the value of the captured baseband signal sample.

Abstract: To estimate complex factors for use in predistortion of a power amplifier, a complex factor is selected a set of complex factors a computation interval. A solution value is estimated for the selected complex factor during the computation interval by an iterative computation that constrains the estimated solution value towards a final solution value over an arbitrary number of iterations that is not bounded by the duration of the computation interval. A cumulative error in the estimated solution value is computed at each iteration over consecutive computation intervals. From the cumulative error, it is determined whether a convergence criterion is met and, if so, the estimating is terminated. The termination occurs independently of the solution value estimated for any one of the complex factors in the set.

Abstract: A transceiver includes an input node to receive an input signal having in-phase (I) data and quadrature (Q) data, the input signal including several data samples. A correlation module determines an autocorrelation of the in-phase data, an autocorrelation of the quadrature data, a difference between the autocorrelation of the in-phase data and the autocorrelation of the quadrature data, and a cross correlation between the in-phase data and the quadrature data. An averaging module determines an average of the difference between the autocorrelation of the in-phase data and the autocorrelation of the quadrature data, and an average of the cross correlation between the in-phase data and the quadrature data, in which the averages are determined over a specified number of data samples.

Abstract: To estimate complex factors for use in predistortion of a power amplifier, a complex factor is selected a set of complex factors a computation interval. A solution value is estimated for the selected complex factor during the computation interval by an iterative computation that constrains the estimated solution value towards a final solution value over an arbitrary number of iterations that is not bounded by the duration of the computation interval. A cumulative error in the estimated solution value is computed at each iteration over consecutive computation intervals. From the cumulative error, it is determined whether a convergence criterion is met and, if so, the estimating is terminated. The termination occurs independently of the solution value estimated for any one of the complex factors in the set.

Abstract: A baseband signal is generated as a sequence of complex sample values at a predetermined sample rate. A sample of the baseband signal is captured as is a sample of an output signal generated by a power amplifier from the captured sample of the baseband signal. Complex values are iteratively assigned to a complex factor intended for predistorting data such that the product of the baseband signal sample and the complex factor converges towards equivalence with the output signal sample with each iterative assignment of the complex values to the complex factor. The complex factor is stored in memory at an address associated with the value of the captured baseband signal sample.