Abstract: A dual-edge triggered variable frequency divider for use in digital frequency synthesis is disclosed. The variable frequency divider utilizes a multiphase clock and a logic unit, including both positive and negative edge triggered unit delay elements connected in parallel. The variable frequency divider generates a clock pulse from a signal source that corresponds to an input value from a logic unit, generates a next input value by the logic unit based on the input value and a frequency control word, and transmits the next input value from the logic unit to the signal source in response to the clock pulse. The multiphase clock is configured to generate the clock signal in response to the falling edge of the first pulse of the clock signal.

Abstract: A communication system including a configurable sample rate converter and a controller is provided. The configurable sample rate converter, configured to convert a digital signal with a first sample rate to a converted signal with a second sample rate, being operable in one of a first configuration and a second configuration. The controller, configured to dynamically control the sample rate converter to operate in one of the first configuration and the second configuration according to at least one condition.

Abstract: A transceiver includes an input node to receive an input signal having in-phase (I) data and quadrature (Q) data, the input signal including several data samples. A correlation module determines an autocorrelation of the in-phase data, an autocorrelation of the quadrature data, a difference between the autocorrelation of the in-phase data and the autocorrelation of the quadrature data, and a cross correlation between the in-phase data and the quadrature data. An averaging module determines an average of the difference between the autocorrelation of the in-phase data and the autocorrelation of the quadrature data, and an average of the cross correlation between the in-phase data and the quadrature data, in which the averages are determined over a specified number of data samples.

Abstract: A communications device includes a plurality of wireless transmitters operable at different respective frequencies and each configured to generate respective IQ signals having an initial IQ imbalance. An auxiliary receiver is coupled to a given wireless transmitter. In addition, a controller is configured to apply predistortion to the each wireless transmitter of the plurality thereof based upon the initial IQ imbalance generated by the given wireless transmitter to reduce the initial IQ imbalance in each wireless transmitter.

Abstract: A communications device includes a plurality of wireless transmitters operable at different respective frequencies and each configured to generate respective IQ signals having an initial IQ imbalance. The communications device also includes a frequency tunable auxiliary receiver, and a controller. The controller is configured to selectively couple a given wireless transmitter to the frequency tunable auxiliary receiver and tune the frequency tunable auxiliary receiver to a frequency of the given wireless transceiver, and apply predistortion to the given wireless transmitter based upon the initial IQ imbalance to reduce the initial IQ imbalance.

Abstract: A reconfigurable circuit block includes a rate-conversion circuit, a processing circuit, a first asynchronous interface circuit, and a second asynchronous interface circuit. The rate-conversion circuit converts a first input signal into a first output signal. The processing circuit processes a second input signal to generate a second output signal. The first asynchronous interface circuit outputs a third output signal asynchronous with the first output signal. The second asynchronous interface circuit outputs a fourth output signal asynchronous with the second output signal. The controllable interconnection circuit transmits the third output signal to the processing circuit to serve as the second input signal when controlled to have a first interconnection configuration, and transmits the fourth output signal to the rate-conversion circuit to serve as the first input signal when controlled to have a second interconnection configuration.

Abstract: A digital transmitter includes: a plurality of converting devices arranged to generate a plurality of converting signals according to a plurality of digital input signals; a compensation device arranged to generate at least one compensation signal according to the plurality of digital input signals; and a combining circuit arranged to output an amplified output signal according to the plurality of converting signals and the at least one compensation signal.

Abstract: A digital transmitter includes: a plurality of adjustable delay lines arranged to delay a plurality of digital input signals by a plurality of delay times to generate a plurality of delayed digital input signals respectively; a plurality of converting devices arranged to convert the plurality of delayed digital input signals into a plurality of converting signals respectively; and a calibration device arranged to adjust a delay time of at least one adjustable delay line in the plurality of adjustable delay lines to make the plurality of converting devices convert the plurality of delayed digital input signals at respective desire time points.

Abstract: A modulator generates a baseband digital signal from an information-bearing digital signal. The baseband signal has time-varying phase and amplitude defined by a sequence of complex data words, each having an in-phase (I) component and a quadrature (Q) component. A noise-shaping modulator generates a noise-shaped digital signal from the baseband digital signal such that quantization noise in the noise-shaping modulator is attenuated by a spectral null of its noise transfer function. The spectral null is selected by a noise-shaping parameter corresponding to a selected one of a plurality of output frequencies. A signal converter generates an analog signal conveying the information of the information-bearing digital signal on an analog carrier signal having the selected output frequency.

Abstract: A dual-edge triggered variable frequency divider for use in digital frequency synthesis is disclosed. The variable frequency divider utilizes a multiphase clock and a logic unit, including both positive and negative edge triggered unit delay elements connected in parallel. The variable frequency divider generates a clock pulse from a signal source that corresponds to an input value from a logic unit, generates a next input value by the logic unit based on the input value and a frequency control word, and transmits the next input value from the logic unit to the signal source in response to the clock pulse. The multiphase clock is configured to generate the clock signal in response to the falling edge of the first pulse of the clock signal.

Abstract: Direct digital frequency synthesis is the process by which a digital frequency synthesizer component may output a stable, precise clock frequency at any of a broad range of possible frequency output values for any number of applications, usually across an integrated circuit. The digital frequency synthesizer set forth in this disclosure is a combination of a controller configured to receive a frequency control word and generate a first frequency control sub-word and a second frequency control sub-word based on the frequency control word, a frequency generator configured to generate a source frequency within a first predetermined frequency range based on the first frequency control sub-word, and a variable frequency divider configured to generate an output frequency within a second predetermined range based on the second frequency control sub-word and the source frequency.

Abstract: A predistortion function is evaluated with in-phase (I) and quadrature (Q) data words as arguments, while additive I and Q data words are generated in accordance with a comparison of the I and Q data words with a full scale value that generates maximum current in a digital power amplifier. The additive I and Q data words are added to the computed I and Q data words to produce predistorted I and Q data words. The predistorted I and Q data words are provided in a sequence to the digital power amplifier, which generates a corresponding radio-frequency (RF) analog signal.

Abstract: A communications device includes a baseband input to receive a baseband signal. A transmitter is coupled to the baseband input and generates a transmit signal based upon the baseband signal, the transmit signal having an initial transmit impairment. An auxiliary receiver is coupled to the transmitter and generates a receive signal having a receive impairment therein resulting from the initial transmit impairment. A controller determines a power of the baseband signal by integrating a product of the receive signal and a complex conjugate of the baseband signal, and determines a power of the receive signal by integrating a product of the baseband signal and the receive signal. The controller also determines the initial transmit impairment based upon the power of the baseband signal and the receive signal, and generates a transmit impairment compensation signal based upon the initial transmit impairment.

Abstract: A mobile wireless communications device includes a transceiver comprising a transmitter and a receiver, an auxiliary receiver, and a controller. The transmitter is configured to upconvert a transmit baseband modulated signal and generate an RF modulated signal having a transmit impairment. The auxiliary receiver is configured to downconvert the RF modulated signal and generate a receive baseband modulated signal having the transmit impairment. The auxiliary receiver is selectively configured to operate based on a control signal in a single-mixer mode when the transmitter is selectively configured to operate in a dual-mixer mode, and in the dual-mixer mode when the transmitter is selectively configured to operate in the single-mixer mode. The controller is configured to compare the transmit baseband modulated signal to the transmit impairment to determine an error difference therebetween, and generate the control signal based on the error difference.

Abstract: Provided is an apparatus comprising a DCDC converter having a plurality of converter modules each configured to convert current from a first voltage level to another voltage form. In accordance with an embodiment of the disclosure, the converter modules are configured to be dynamically enabled or disabled such that only each converter module that has been enabled converts current for an output of the DCDC converter. Any inefficiency that would have been introduced by converter modules that are not needed are mitigated or eliminated altogether. The effect is that efficiency can be improved during low load conditions when there is no need to enable all of the converter modules.

Abstract: In one embodiment, a sequence of a plurality of pairs of in-phase (I) and quadrature (Q) modulated signal samples are applied to a radio frequency digital-to-analog converter (RFDAC) for upconversion. A phase of a local oscillator (LO) signal supplied to the RFDAC is selected according to a quadrant determined by signs of a given pair of I and Q modulated signal samples. The selected phase of the LO is supplied to the RFDAC for use in upconverting the sequence of I and Q modulated signal samples. In another embodiment, a current steering DAC is used for directly upconverting the I and Q modulated signal samples. A clock signal at four times the LO frequency is supplied to a counter and to the current steering DAC. One of the I and Q modulated signal samples and negative I and negative Q modulated signal samples is selected for supply to an input of the current steering DAC based on a count state of the counter.

Abstract: Aspects of the disclosure provide a transmitter that includes a pre-distortion module and a phase controller. The pre-distortion module is configured to receive a first digital value and generate a first pre-distorted digital value based on the first digital value and a corresponding angle. The first digital value is a combination of an in-phase component and a quadrature component of a signal for transmission. The phase controller is configured to control an amplifier to drive a current according to the first pre-distorted digital value and phase information in relation to the first digital value during a first phase range of a carrier signal determined at least partially based on the angle.

Abstract: In one embodiment, a sequence of a plurality of pairs of in-phase (I) and quadrature (Q) modulated signal samples are applied to a radio frequency digital-to-analog converter (RFDAC) for upconversion. A phase of a local oscillator (LO) signal supplied to the RFDAC is selected according to a quadrant determined by signs of a given pair of I and Q modulated signal samples. The selected phase of the LO is supplied to the RFDAC for use in upconverting the sequence of I and Q modulated signal samples. In another embodiment, a current steering DAC is used for directly upconverting the I and Q modulated signal samples. A clock signal at four times the LO frequency is supplied to a counter and to the current steering DAC. One of the I and Q modulated signal samples and negative I and negative Q modulated signal samples is selected for supply to an input of the current steering DAC based on a count state of the counter.

Abstract: A modulator generates a baseband digital signal from an information-bearing digital signal. The baseband signal has time-varying phase and amplitude defined by a sequence of complex data words, each having an in-phase (I) component and a quadrature (Q) component. A noise-shaping modulator generates a noise-shaped digital signal from the baseband digital signal such that quantization noise in the noise-shaping modulator is attenuated by a spectral null of its noise transfer function. The spectral null is selected by a noise-shaping parameter corresponding to a selected one of a plurality of output frequencies. A signal converter generates an analog signal conveying the information of the information-bearing digital signal on an analog carrier signal having the selected output frequency.

Abstract: A communications device includes a housing and a wireless transceiver and processor carried by the housing and operative with each other. An input screen is carried by the housing and comprises a plurality of spaced transceivers positioned at the input screen and connected to the processor and each configured to transmit a millimeter wave RF signal and receive reflected signals from an object positioned close to the input screen. The processor is configured to determine the location of the object relative to the input screen based on the reflected signals received at each transceiver.