Patents by Inventor Khushali Shah

Khushali Shah has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220216833
    Abstract: Circuits and methods for improving the noise figure (NF) of an amplifier, particularly an LNA, in high-gain modes while improving the IIP3 of the amplifier in low-gain modes. The source of an amplifier common-source FET is coupled to circuit ground thorough a degeneration circuit comprising a two-port inductor and a bypass switch coupled in parallel with the inductor. A switched feedback circuit is coupled between the gate of the common-source FET and a feedback node in the amplifier output signal path. During a low gain mode, the inductor is entirely bypassed and the enabled feedback circuit lowers the input impedance of the common-source FET and reduces the gain of the amplifier circuit, essentially eliminating the need for a degeneration inductor. During a high gain mode, the source of the common-source FET is coupled to circuit ground through the inductor and the feedback circuit is disabled. Other gain modes are supported.
    Type: Application
    Filed: January 5, 2021
    Publication date: July 7, 2022
    Inventors: Rong Jiang, Khushali Shah, Ravindranath D. Shrivastava, Parvez Daruwalla
  • Patent number: 11356068
    Abstract: Compact low noise amplifiers that have wide-band coverage while meeting necessary input matching and output matching characteristics. Embodiments include a wide-band, two-stage LNA with minimum degradation in performance compared to multiple narrow-band, single-stage LNAs. A generalized embodiment includes a first amplifier stage having a terminal coupled to a mutually coupled inductor circuit and to a second amplifier stage. The second amplifier stage includes a terminal coupled to the mutually coupled inductor circuit. The mutually coupled inductor circuit comprises electromagnetically coupled inductors L1, L2. Second terminals of the first and second amplifier stages are coupled to respective degeneration inductors. The electromagnetically coupled inductors L1, L2 of the inductor circuit substantially increase the output bandwidth of the LNA with minimum degradation in performance.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: June 7, 2022
    Assignee: pSemi Corporation
    Inventors: Rong Jiang, Khushali Shah
  • Publication number: 20220109410
    Abstract: Circuits and methods for generating a bypass pulse to an RF circuit that increases the response time of the circuit to mode changes. Embodiments include a pulse generation circuit that it is self-initiated and self-terminated, generating a bypass pulse as a function of voltages V1 and V2 along a signal path. Voltage V3, a scaled version of V1, is compared to a voltage V4 derived from V2 and a pulse is output while V3>V4. The pulse temporarily lowers the signal path impedance, reducing the RC time constant of the signal path and allowing fast charging of components coupled to the signal path. The pulse may be used with any other circuit that needs a faster settling time after a mode change but is slowed down by an RC time constant. Usage also extends to providing for rapid discharge of the signal path by adding additional logic components.
    Type: Application
    Filed: October 1, 2020
    Publication date: April 7, 2022
    Inventors: Yucheng Tong, Ping Wing Lai, Khushali Shah
  • Publication number: 20220077827
    Abstract: Circuit and methods using a single low-noise amplifier (LNA) to provide amplification for a wide band of RF frequencies while maintaining high gain and a low noise factor. Embodiments include an amplifier circuit including an input signal path for receiving a wideband RF signal; a switched inductor tuning block coupled to the input signal path and configured to selectively couple one of a plurality of inductances to the input signal path; and an amplifier coupled to the switched inductor tuning block and configured to receive the RF signal after passage through the selected coupled inductance. The switched inductor tuning block includes a plurality of selectable branches, each including an RF input switch; an RF output switch; an inductor coupled between the RF input switch and the RF output switch; and first and second shunt switches coupled between a respective terminal of the inductor and circuit ground.
    Type: Application
    Filed: September 10, 2020
    Publication date: March 10, 2022
    Inventors: Rong Jiang, Khushali Shah
  • Publication number: 20220021354
    Abstract: Compact low noise amplifiers that have wide-band coverage while meeting necessary input matching and output matching characteristics. Embodiments include a wide-band, two-stage LNA with minimum degradation in performance compared to multiple narrow-band, single-stage LNAs. A generalized embodiment includes a first amplifier stage having a terminal coupled to a mutually coupled inductor circuit and to a second amplifier stage. The second amplifier stage includes a terminal coupled to the mutually coupled inductor circuit. The mutually coupled inductor circuit comprises electromagnetically coupled inductors L1, L2. Second terminals of the first and second amplifier stages are coupled to respective degeneration inductors. The electromagnetically coupled inductors L1, L2 of the inductor circuit substantially increase the output bandwidth of the LNA with minimum degradation in performance.
    Type: Application
    Filed: July 14, 2020
    Publication date: January 20, 2022
    Inventors: Rong Jiang, Khushali Shah
  • Publication number: 20220014221
    Abstract: A clamping circuit that may be used to provide efficient and effective voltage clamping in an RF front end. The clamping circuit comprises two series coupled signal path switches and a bypass switch coupled in parallel with the series coupled signal path switches. A diode is coupled from a point between the series coupled signal path switches to a reference potential. In addition, an output selection switch within an RF front end has integrated voltage clamping to more effectively clamp the output voltage from the RF front end. Additional output clamping circuits can be used at various places along a direct gain signal path, along an attenuated gain path and along a bypass path.
    Type: Application
    Filed: July 23, 2021
    Publication date: January 13, 2022
    Inventors: Rong Jiang, Khushali Shah, Peter Bacon
  • Patent number: 11075661
    Abstract: A clamping circuit that may be used to provide efficient and effective voltage clamping in an RF front end. The clamping circuit comprises two series coupled signal path switches and a bypass switch coupled in parallel with the series coupled signal path switches. A diode is coupled from a point between the series coupled signal path switches to a reference potential. In addition, an output selection switch within an RF front end has integrated voltage clamping to more effectively clamp the output voltage from the RF front end. Additional output clamping circuits can be used at various places along a direct gain signal path, along an attenuated gain path and along a bypass path.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: July 27, 2021
    Assignee: pSemi Corporation
    Inventors: Rong Jiang, Khushali Shah, Peter Bacon
  • Patent number: 11025208
    Abstract: Methods and devices for amplifying a plurality of input RF signals based on a multi-input cascode configuration is described. Transistors of stages of the multi-input cascode configuration are connected according to a tree, where there is at least one cascode transistor that is connected to at least two transistors of a stage below. In one case the stage below is an input stage, and in another case the stage below is a cascode stage. Activation and deactivation of transistors of the stages provide different conduction paths between the input stage and an output stage.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: June 1, 2021
    Assignee: pSemi Corporation
    Inventors: Khushali Shah, Haopei Deng
  • Publication number: 20200127617
    Abstract: Methods and devices for amplifying a plurality of input RF signals based on a multi-input cascode configuration is described. Transistors of stages of the multi-input cascode configuration are connected according to a tree, where there is at least one cascode transistor that is connected to at least two transistors of a stage below. In one case the stage below is an input stage, and in another case the stage below is a cascode stage. Activation and deactivation of transistors of the stages provide different conduction paths between the input stage and an output stage.
    Type: Application
    Filed: September 27, 2019
    Publication date: April 23, 2020
    Inventors: Khushali Shah, Haopei Deng
  • Patent number: 10461704
    Abstract: Methods and devices for amplifying a plurality of input RF signals based on a multi-input cascode configuration is described. Transistors of stages of the multi-input cascode configuration are connected according to a tree, where there is at least one cascode transistor that is connected to at least two transistors of a stage below. In one case the stage below is an input stage, and in another case the stage below is a cascode stage. Activation and deactivation of transistors of the stages provide different conduction paths between the input stage and an output stage.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: October 29, 2019
    Assignee: pSemi Corporation
    Inventors: Khushali Shah, Haopei Deng
  • Publication number: 20190190468
    Abstract: Methods and devices for amplifying a plurality of input RF signals based on a multi-input cascode configuration is described. Transistors of stages of the multi-input cascode configuration are connected according to a tree, where there is at least one cascode transistor that is connected to at least two transistors of a stage below. In one case the stage below is an input stage, and in another case the stage below is a cascode stage. Activation and deactivation of transistors of the stages provide different conduction paths between the input stage and an output stage.
    Type: Application
    Filed: December 18, 2017
    Publication date: June 20, 2019
    Inventors: Khushali Shah, Haopei Deng