Abstract: In a display panel and a method of manufacturing the display panel, the display panel includes a display substrate including a first electrode and a second electrode insulated from the first electrode and disposed on the first electrode, an opposite substrate including a third electrode facing the second electrode, and a liquid crystal layer interposed between the display substrate and the opposite substrate. The liquid crystal layer includes liquid crystal molecules, a reactive mesogen polymer, and nano-rods.

Abstract: In a display panel and a method of manufacturing the display panel, the display panel includes a display substrate including a first electrode and a second electrode insulated from the first electrode and disposed on the first electrode, an opposite substrate including a third electrode facing the second electrode, and a liquid crystal layer interposed between the display substrate and the opposite substrate. The liquid crystal layer includes liquid crystal molecules, a reactive mesogen polymer, and nano-rods.

Abstract: A module control circuit includes an input unit configured to receive a plurality of data signals from a plurality of data input/output pins and output an identification signal and an internal command signal. A latch unit is configured to latch the identification signal in accordance with a first enable signal to output a first group identification signal, latch the identification signal in accordance with a second enable signal to output a second group identification signal, and latch the internal command signal in accordance with the second enable signal to output a group command signal. A comparator is configured to compare the first group identification signal with the second group identification signal, and generate a selection signal. A multiplexer is configured to select one of the group command signal and a module command signal as an input command in response to the selection signal.

Abstract: A semiconductor apparatus includes a power supply changing unit. The power supply changing unit is configured to receive an enable signal and power supply voltage, generate first voltage or second voltage according to the enable signal, change a voltage level of the second voltage according to a level signal, and supply the first voltage or the second voltage as a driving voltage of an internal circuit, wherein the internal circuit receives a first input signal to output a second input signal.

Abstract: A comparator circuit includes a first comparator configured to store an offset during a first period, and to compare first and second input signals while compensating for the stored offset to generate a first comparison signal during a second period, a second comparator configured to compare the first and second input signals while compensating for an offset to generate a second comparison signal, and a compensation amount controller configured to control an offset compensation amount of the second comparator when the first and second comparison signals have different values.

Abstract: A comparator circuit includes a first comparator configured to store an offset during a first period, and to compare first and second input signals while compensating for the stored offset to generate a first comparison signal during a second period, a second comparator configured to compare the first and second input signals while compensating for an offset to generate a second comparison signal, and a compensation amount controller configured to control an offset compensation amount of the second comparator when the first and second comparison signals have different values.

Abstract: A liquid crystal display panel includes a lower substrate, an upper substrate and a liquid crystal layer. The lower substrate includes a first base substrate and a pixel electrode formed on the first base substrate. The first base substrate includes a first sub pixel area and a second sub pixel area. The upper substrate includes a second base substrate and a common electrode formed on the second base substrate. The liquid crystal layer is interposed between the lower substrate and the upper substrate, and includes a first polymer disposed in the first sub pixel area and a second polymer disposed in the second pixel area. The first polymer has a first pre-tilt, and the second polymer has a second pre-tilt different from the first pre-tilt. Thus, a display quality of a liquid crystal display apparatus including the liquid crystal display panel may be enhanced.

Abstract: A phase control circuit includes a first duty cycle correction circuit configured to correct a duty cycle of a clock signal; a delay locked loop configured to perform delay locking of an output signal of the first duty cycle correction circuit; and a second duty cycle correction circuit configured to correct a duty cycle of an output signal of the delay locked loop, wherein the first duty cycle correction circuit and the second duty cycle correction circuit are selectively activated depending upon an operating condition.

Abstract: A module control circuit includes an input unit configured to receive a plurality of data signals from a plurality of data input/output pins and output an identification signal and an internal command signal. A latch unit is configured to latch the identification signal in accordance with a first enable signal to output a first group identification signal, latch the identification signal in accordance with a second enable signal to output a second group identification signal, and latch the internal command signal in accordance with the second enable signal to output a group command signal. A comparator is configured to compare the first group identification signal with the second group identification signal, and generate a selection signal. A multiplexer is configured to select one of the group command signal and a module command signal as an input command in response to the selection signal.

Abstract: A transflective liquid crystal display includes a liquid crystal panel including a first substrate, a second substrate, a liquid crystal layer, the first and second substrates arranged to face each other and the liquid crystal layer between the first and second substrates, a reflection polarizer and an absorption polarizer at opposing outer sides of the liquid crystal panel, and a backlight unit at an outer side of the liquid crystal panel and supplying light to the inside of the liquid crystal panel. A reflective axis of the reflection polarizer is parallel with a transmissive axis of the absorption polarizer, the transmissive axis of the reflection polarizer perpendicularly crosses the transmissive axis of the absorption polarize, and the liquid crystal layer includes liquid crystal molecules and a dichroic dye.

Abstract: A duty cycle correction circuit includes: a duty cycle correction unit configured to correct a duty cycle of an input clock signal according to a duty cycle correction code and generate an output clock signal; a duty cycle detection section configured to detect a duty cycle of the output clock signal and generate an up-down signal; a noise detection signal generation section configured to detect a variation of the up-down signal and generate the noise detection signal; and a duty cycle correction control unit configured to generate the duty cycle correction code in response to the noise detection signal and the up-down signal.

Abstract: A device characteristic compensation circuit includes a device characteristic detection block configured to detect one or more of a frequency of a clock signal and characteristics of devices, and generate a control code signal according to a detection result; and an internal voltage regulation unit configured to regulate a level of an internal voltage in response to the control code signal and generate a corrected internal voltage.

Abstract: A liquid crystal display is provided. A liquid crystal display according to an exemplary embodiment of the present invention includes a first substrate, a second substrate facing the first substrate, and a liquid crystal layer interposed between the first substrate and the second substrate, wherein the liquid crystal layer includes liquid crystal molecules and nanoparticles including a hydrophobic group having a chain structure and a hydrophilic group.

Abstract: A data output control circuit includes a DLL circuit and a delay detection unit. The DLL circuit is configured to generate a second internal clock by delaying a first internal clock generated from an external clock, compare a phase of the first internal clock with a phase of the second internal clock, and generate a DLL clock. The delay detection unit is configured to generate a sense signal whose logic level is changed according to a comparison result of a set time interval and a delay time interval during which the first internal clock is delayed in order to generate the second internal clock.

Abstract: A duty cycle correction circuit includes: a duty cycle correction unit configured to correct a duty cycle of an input clock signal according to a duty cycle correction code and generate an output clock signal; a duty cycle detection section configured to detect a duty cycle of the output clock signal and generate an up-down signal; a noise detection signal generation section configured to detect a variation of the up-down signal and generate the noise detection signal; and a duty cycle correction control unit configured to generate the duty cycle correction code in response to the noise detection signal and the up-down signal.

Abstract: A semiconductor apparatus includes a power supply changing unit. The power supply changing unit is configured to receive an enable signal and power supply voltage, generate first voltage or second voltage according to the enable signal, change a voltage level of the second voltage according to a level signal, and supply the first voltage or the second voltage as a driving voltage of an internal circuit, wherein the internal circuit receives a first input signal to output a second input signal.

Abstract: An output enable signal generation circuit includes a latency decoder, a latch unit, a latency multiplexer, and an enable setting unit. The latency decoder is configured to decode a mode register set code and generate first and second CAS latency information. The latch unit is configured to output the latched first and second latency information as first and second latency signals. The latency multiplexer is configured to output the first or second latency signal as an output CAS latency signal in response to a chip select signal. The enable setting unit is configured to set an enable timing of an output enable signal.

Abstract: In a display panel and a method of manufacturing the display panel, the display panel includes a display substrate including a first electrode and a second electrode insulated from the first electrode and disposed on the first electrode, an opposite substrate including a third electrode facing the second electrode, and a liquid crystal layer interposed between the display substrate and the opposite substrate. The liquid crystal layer includes liquid crystal molecules, a reactive mesogen polymer, and nano-rods.

Abstract: A semiconductor apparatus for generating an internal voltage includes a control code output block and an internal voltage generation block. The control code output block is configured to output a variable code having a code value corresponding to a voltage level of an internal voltage. The internal voltage generation block is configured to compare the variable code to a setting code and controls the voltage level of the internal voltage according to the comparison.

Abstract: A semiconductor apparatus includes: an update pulse generating unit configured to generate an update pulse every first period based on a frequency of a clock, and a control unit configured to control an output signal in response to an input signal and the update pulse, so that the output signal is varied based on the input signal.