Abstract: A module control circuit includes an input unit configured to receive a plurality of data signals from a plurality of data input/output pins and output an identification signal and an internal command signal. A latch unit is configured to latch the identification signal in accordance with a first enable signal to output a first group identification signal, latch the identification signal in accordance with a second enable signal to output a second group identification signal, and latch the internal command signal in accordance with the second enable signal to output a group command signal. A comparator is configured to compare the first group identification signal with the second group identification signal, and generate a selection signal. A multiplexer is configured to select one of the group command signal and a module command signal as an input command in response to the selection signal.

Abstract: A clock receiver in a semiconductor integrated circuit includes a first clock buffer configured to buffer an external clock to generate a low frequency buffered clock in response to a first operation signal; a second clock buffer configured to buffer the external clock to generate a high frequency buffered clock in response to a second operation signal; and an internal clock generating unit configured to receive the low frequency buffered clock and the high frequency buffered clock, to control states of the first operation signal and the second operation signal and to generate an internal clock.

Abstract: A clock generation circuit of a semiconductor apparatus includes a first phase detection block configured to compare initial phases of a reference clock signal and an output clock signal in response to an operation start signal, and output an initial phase difference detection signal corresponding to a comparison result; a second phase detection block configured to compare phases of the reference clock signal and the output clock signal, and output a phase detection signal corresponding to a comparison result; a variable unit delay block determined in a control range of the delay amount thereof in response to the initial phase difference detection signal, and configured to delay the reference clock signal by a delay amount corresponding to a voltage level of a control voltage and output the output clock signal; and a delay control block configured to generate the control voltage which has the voltage level corresponding to the phase detection signal.

Abstract: A phase control circuit includes a first duty cycle correction circuit configured to correct a duty cycle of a clock signal; a delay locked loop configured to perform delay locking of an output signal of the first duty cycle correction circuit; and a second duty cycle correction circuit configured to correct a duty cycle of an output signal of the delay locked loop, wherein the first duty cycle correction circuit and the second duty cycle correction circuit are selectively activated depending upon an operating condition.

Abstract: A transflective liquid crystal display includes a liquid crystal panel including a first substrate, a second substrate, a liquid crystal layer, the first and second substrates arranged to face each other and the liquid crystal layer between the first and second substrates, a reflection polarizer and an absorption polarizer at opposing outer sides of the liquid crystal panel, and a backlight unit at an outer side of the liquid crystal panel and supplying light to the inside of the liquid crystal panel. A reflective axis of the reflection polarizer is parallel with a transmissive axis of the absorption polarizer, the transmissive axis of the reflection polarizer perpendicularly crosses the transmissive axis of the absorption polarize, and the liquid crystal layer includes liquid crystal molecules and a dichroic dye.

Abstract: A device characteristic compensation circuit includes a device characteristic detection block configured to detect one or more of a frequency of a clock signal and characteristics of devices, and generate a control code signal according to a detection result; and an internal voltage regulation unit configured to regulate a level of an internal voltage in response to the control code signal and generate a corrected internal voltage.

Abstract: A duty correction circuit is presented for use in compensating for a duty rate error brought about when a malfunction of a clock signal generator or a failure of a signal transmission line occurs. The duty correction circuit is configured to select one of differential signals as an input signal according to a duty rate. The duty correction circuit is also configured to combine the input signal and a signal obtained by delaying the input signal by a delay time adjusted in accordance to the duty rate. The duty correction circuit is also configured to generate the combined signal as a duty correction signal.

Abstract: Various embodiments of a semiconductor integrated circuit. According to one exemplary embodiment, a semiconductor integrated circuit includes a multi-phase clock generator that is configured to generate a multi-phase internal clock; a first edge combining unit that is configured to generate a first output clock having a first frequency by combining rising edges of clocks included in the internal clock, and transmit the first output clock to a first port; and a second edge combining unit that is configured to generate a second output clock having a second frequency by combining rising edges of clocks included in the internal clock, and transmit the output clock to a second port.

Abstract: A semiconductor apparatus includes: an update pulse generating unit configured to generate an update pulse every first period based on a frequency of a clock, and a control unit configured to control an output signal in response to an input signal and the update pulse, so that the output signal is varied based on the input signal.

Abstract: An output enable signal generation circuit includes a latency decoder, a latch unit, a latency multiplexer, and an enable setting unit. The latency decoder is configured to decode a mode register set code and generate first and second CAS latency information. The latch unit is configured to output the latched first and second latency information as first and second latency signals. The latency multiplexer is configured to output the first or second latency signal as an output CAS latency signal in response to a chip select signal. The enable setting unit is configured to set an enable timing of an output enable signal.

Abstract: A module control circuit includes an input unit configured to receive a plurality of data signals from a plurality of data input/output pins and output an identification signal and an internal command signal. A latch unit is configured to latch the identification signal in accordance with a first enable signal to output a first group identification signal, latch the identification signal in accordance with a second enable signal to output a second group identification signal, and latch the internal command signal in accordance with the second enable signal to output a group command signal. A comparator is configured to compare the first group identification signal with the second group identification signal, and generate a selection signal. A multiplexer is configured to select one of the group command signal and a module command signal as an input command in response to the selection signal.

Abstract: A data output control circuit includes a DLL circuit and a delay detection unit. The DLL circuit is configured to generate a second internal clock by delaying a first internal clock generated from an external clock, compare a phase of the first internal clock with a phase of the second internal clock, and generate a DLL clock. The delay detection unit is configured to generate a sense signal whose logic level is changed according to a comparison result of a set time interval and a delay time interval during which the first internal clock is delayed in order to generate the second internal clock.

Abstract: A clock generation circuit of a semiconductor apparatus includes a first phase detection block configured to compare initial phases of a reference clock signal and an output clock signal in response to an operation start signal, and output an initial phase difference detection signal corresponding to a comparison result; a second phase detection block configured to compare phases of the reference clock signal and the output clock signal, and output a phase detection signal corresponding to a comparison result; a variable unit delay block determined in a control range of the delay amount thereof in response to the initial phase difference detection signal, and configured to delay the reference clock signal by a delay amount corresponding to a voltage level of a control voltage and output the output clock signal; and a delay control block configured to generate the control voltage which has the voltage level corresponding to the phase detection signal.

Abstract: A semiconductor apparatus for generating an internal voltage includes a control code output block and an internal voltage generation block. The control code output block is configured to output a variable code having a code value corresponding to a voltage level of an internal voltage. The internal voltage generation block is configured to compare the variable code to a setting code and controls the voltage level of the internal voltage according to the comparison.

Abstract: A duty correction circuit is presented for use in compensating for a duty rate error brought about when a malfunction of a clock signal generator or a failure of a signal transmission line occurs. The duty correction circuit is configured to select one of differential signals as an input signal according to a duty rate. The duty correction circuit is also configured to combine the input signal and a signal obtained by delaying the input signal by a delay time adjusted in accordance to the duty rate. The duty correction circuit is also configured to generate the combined signal as a duty correction signal.

Abstract: A semiconductor integrated circuit includes a frequency determining unit configured to determine an operational speed of the semiconductor integrated circuit and to generate a frequency region signal; a duty cycle control unit configured to detect a duty cycle of a DLL clock and to generate a duty cycle control signal; a duty cycle correcting unit configured to generate a corrected clock by correcting a duty cycle of an input clock in response to the frequency region signal and in response to the duty cycle control signal; and a DLL (Delay Locked Loop) circuit configured to generate the DLL clock by controlling a phase of the corrected clock.

Abstract: Various embodiments of a semiconductor integrated circuit. According to one exemplary embodiment, a semiconductor integrated circuit includes a multi-phase clock generator that is configured to generate a multi-phase internal clock; a first edge combining unit that is configured to generate a first output clock having a first frequency by combining rising edges of clocks included in the internal clock, and transmit the first output clock to a first port; and a second edge combining unit that is configured to generate a second output clock having a second frequency by combining rising edges of clocks included in the internal clock, and transmit the output clock to a second port.

Abstract: A clock receiver in a semiconductor integrated circuit includes a first clock buffer configured to buffer an external clock to generate a low frequency buffered clock in response to a first operation signal; a second clock buffer configured to buffer the external clock to generate a high frequency buffered clock in response to a second operation signal; and an internal clock generating unit configured to receive the low frequency buffered clock and the high frequency buffered clock, to control states of the first operation signal and the second operation signal and to generate an internal clock.

Abstract: A semiconductor integrated circuit includes a frequency determining unit configured to determine an operational speed of the semiconductor integrated circuit and to generate a frequency region signal; a duty cycle control unit configured to detect a duty cycle of a DLL clock and to generate a duty cycle control signal; a duty cycle correcting unit configured to generate a corrected clock by correcting a duty cycle of an input clock in response to the frequency region signal and in response to the duty cycle control signal; and a DLL (Delay Locked Loop) circuit configured to generate the DLL clock by controlling a phase of the corrected clock.