Abstract: A transparent display for a vehicle that includes a self-emissive display with an electronically adjustable brightness and a masking display with an electronically adjustable absorption. The masking display is arranged back-to-back with the self-emissive display. At least one light sensor that is arranged in proximity to the masking display. A display controller is connected to the self-emissive display, to the masking display and to the at least one light sensor. The display controller is operative to adapt an absorption of the masking display in response to a signal of the at least one light sensor.

Abstract: A transparent display for a vehicle that includes a self-emissive display with an electronically adjustable brightness and a masking display with an electronically adjustable absorption. The masking display is arranged back-to-back with the self-emissive display. At least one light sensor that is arranged in proximity to the masking display. A display controller is connected to the self-emissive display, to the masking display and to the at least one light sensor. The display controller is operative to adapt an absorption of the masking display in response to a signal of the at least one light sensor.

Abstract: An array substrate for a fringe field switching mode liquid crystal display device includes a plurality of gate lines on a substrate; a gate insulating layer on the plurality of gate lines; a plurality of data lines crossing the plurality of gate lines to define a plurality of pixel regions; a thin film transistor electrically connected to the gate and data lines in each pixel region; a pixel electrode having a plate shape in each pixel region, and connected to a portion of the thin film transistor; a first passivation layer on the pixel electrode and over the thin film transistor; and a common electrode on the first passivation layer and having a plurality of openings of a bar shape in each pixel region, wherein a center portion of each opening overlaps the pixel electrode, and both ends along a major axis of each opening protrude beyond the pixel electrode.

Abstract: An array substrate for an in-plane switching mode liquid crystal display device includes: a substrate; a gate line on the substrate; first and second common lines parallel to and spaced apart from the gate line; a data line crossing the gate line to define a pixel region; a thin film transistor connected to the gate line and the data line; a pixel electrode connected to the thin film transistor, the pixel electrode having a plate shape; a plurality of common electrodes connected between the first and second common lines, the plurality of common electrodes overlapping the pixel electrode; and first and second shielding electrodes parallel to the data line, the first and second shielding electrodes spaced apart from each other with respect to the data line.

Abstract: An array substrate for a fringe field switching mode liquid crystal display device includes a plurality of gate lines on a substrate; a gate insulating layer on the plurality of gate lines; a plurality of data lines crossing the plurality of gate lines to define a plurality of pixel regions; a thin film transistor electrically connected to the gate and data lines in each pixel region; a pixel electrode having a plate shape in each pixel region, and connected to a portion of the thin film transistor; a first passivation layer on the pixel electrode and over the thin film transistor; and a common electrode on the first passivation layer and having a plurality of openings of a bar shape in each pixel region, wherein a center portion of each opening overlaps the pixel electrode, and both ends along a major axis of each opening protrude beyond the pixel electrode.

Abstract: A liquid crystal display device includes an array substrate including gate and data line on a first substrate to define first and second sub-pixel regions and a thin film transistor in each of the first and second sub-pixel regions; a color filter substrate including a color filter layer including first and second color filters corresponding to the first and second sub-pixel regions, respectively, a portion of the first color filter overlapping a portion of the second color filter over the data line; and a liquid crystal layer between the array substrate and the color filter substrate.

Abstract: An array substrate for a fringe field switching mode liquid crystal display device includes a plurality of gate lines on a substrate; a gate insulating layer on the plurality of gate lines; a plurality of data lines on the gate insulating layer and crossing the plurality of gate lines to define a plurality of pixel regions; a thin film transistor electrically connected to the gate and data lines and in each pixel region; a pixel electrode having a plate shape and in the each pixel region, the pixel electrode connected to a portion of the thin film transistor; a first passivation layer on the pixel electrode and over the thin film transistor; and a common electrode on the first passivation layer and having a plurality of openings of a bar shape in the each pixel region, each of the openings having a major axis along the data line and a minor axis along the gate line, wherein a center portion of each opening overlaps the pixel electrode, and both ends along the major axis of each opening protrude beyond the pix

Abstract: An array substrate for a fringe field switching mode liquid crystal display device includes a plurality of gate lines on a substrate; a gate insulating layer on the plurality of gate lines; a plurality of data lines on the gate insulating layer and crossing the plurality of gate lines to define a plurality of pixel regions; a thin film transistor electrically connected to the gate and data lines and in each pixel region; a pixel electrode having a plate shape and in the each pixel region, the pixel electrode connected to a portion of the thin film transistor; a first passivation layer on the pixel electrode and over the thin film transistor; and a common electrode on the first passivation layer and having a plurality of openings of a bar shape in the each pixel region, each of the openings having a major axis along the data line and a minor axis along the gate line, wherein a center portion of each opening overlaps the pixel electrode, and both ends along the major axis of each opening protrude beyond the pix

Abstract: An array substrate for an in-plane switching mode liquid crystal display device includes: a substrate; a gate line on the substrate; first and second common lines parallel to and spaced apart from the gate line; a data line crossing the gate line to define a pixel region; a thin film transistor connected to the gate line and the data line; a pixel electrode connected to the thin film transistor, the pixel electrode having a plate shape; a plurality of common electrodes connected between the first and second common lines, the plurality of common electrodes overlapping the pixel electrode; and first and second shielding electrodes parallel to the data line, the first and second shielding electrodes spaced apart from each other with respect to the data line.

Abstract: A liquid crystal display device includes an array substrate including gate and data line on a first substrate to define first and second sub-pixel regions and a thin film transistor in each of the first and second sub-pixel regions; a color filter substrate including a color filter layer including first and second color filters corresponding to the first and second sub-pixel regions, respectively, a portion of the first color filter overlapping a portion of the second color filter over the data line; and a liquid crystal layer between the array substrate and the color filter substrate.

Abstract: The number of mask steps used to fabricate a TFT in an AMLCD is reduced. In particular, source and drain metallizations, as well as doped and undoped semiconductor layers are patterned at the same time, and the source and drain metallizations and the doped semiconductor layer are etched in a single etching step using an insulating passivation layer as a mask to form source and drain electrodes. Manufacturing costs can be reduced and the manufacturing yield can be improved.

Abstract: A thin film transistor is disclosed, including an insulating substrate, a semiconductor layer formed on the insulating substrate, the semiconductor layer having an active region and an impurity region, a gate insulating layer formed on the active region of the semiconductor layer, a first gate metal layer formed on a predetermined portion of the active region of the semiconductor layer to define a channel region, and a second gate metal layer formed on the first gate metal layer. The first and second gate metal layers have different compositions, such that the second gate metal layer etches faster than the first gate metal layer, thereby preventing formation of a hillock. A first protective layer is formed over the structure, then a light shielding layer, and then a second protective layer is formed over the light shielding layer.

Abstract: The number of mask steps used to fabricate a TFT in an AMLCD is reduced. In particular, source and drain metallizations, as well as doped and undoped semiconductor layers are patterned at the same time, and the source and drain metallizations and the doped semiconductor layer are etched in a single etching step using an insulating passivation layer as a mask to form source and drain electrodes. Manufacturing costs can be reduced and the manufacturing yield can be improved.

Abstract: A thin film transistor is disclosed, including an insulating substrate, a semiconductor layer formed on the insulating substrate, the semiconductor layer having an active region and an impurity region, a gate insulating layer formed on the active region of the semiconductor layer, a first gate metal layer formed on a predetermined portion of the active region of the semiconductor layer to define a channel region, and a second gate metal layer formed on the first gate metal layer. The first and second gate metal layers have different compositions, such that the second gate metal layer etches faster than the first gate metal layer, thereby preventing formation of a hillock. A first protective layer is formed over the structure, then a light shielding layer, and then a second protective layer is formed over the light shielding layer.

Abstract: A thin film transistor is disclosed, including an insulating substrate, a semiconductor layer formed on the insulating substrate, the semiconductor layer having an active region and an impurity region, a gate insulating layer formed on the active region of the semiconductor layer, a first gate metal layer formed on a predetermined portion of the active region of the semiconductor layer to define a channel region, and a second gate metal layer formed on the first gate metal layer. The first and second gate metal layers have different compositions, such that the second gate metal layer etches faster than the first gate metal layer, thereby preventing formation of a hillock. A first protective layer is formed over the structure, then a light shielding layer, and then a second protective layer is formed over the light shielding layer.

Abstract: A thin film transistor is disclosed, including an insulating substrate, a semiconductor layer formed on the insulating substrate, the semiconductor layer having an active region and an impurity region, a gate insulating layer formed on the active region of the semiconductor layer, a first gate metal layer formed on a predetermined portion of the active region of the semiconductor layer to define a channel region, and a second gate metal layer formed on the first gate metal layer. The first and second gate metal layers have different compositions, such that the second gate metal layer etches faster than the first gate metal layer, thereby preventing formation of a hillock. A first protective layer is formed over the structure, then a light shielding layer, and then a second protective layer is formed over the light shielding layer.

Abstract: A liquid crystal display device having a plurality of data lines and a plurality of gate lines arranged perpendicular to each other and a plurality of thin film transistors and pixel electrodes formed for respective pixels includes a substrate and a gate electrode on the substrate. A first insulating layer is formed on the substrate and the gate electrode. An active layer is formed on the first insulating layer and an etch stop layer is formed on the active layer over the gate electrode. A silicide layer having first and second sides relative to the second insulating layer is formed on the surface of the active layer and a metal electrode is formed on the first side of the silicide layer. A pixel electrode is formed on the second side of the silicide layer and a third insulating layer is formed having a portion directly on the silicide layer.

Abstract: A liquid crystal display device comprises a substrate, a transparent electrode on the substrate, an anodizing layer and a non-anodizing layer on the transparent electrode, and a thin film transistor over the non-anodizing layer. The anodizing layer is a transparent insulating layer and the non-anodizing layer is an opaque metal layer. These layer are formed by anodizing a metal layer, of which a portion is blocked by a photoresist.

Abstract: A thin film transistor substrate for a liquid crystal display includes a substrate; a thin film transistor over the substrate, the thin film transistor having a gate, a source, a drain, a semiconductor layer, and a gate insulation layer; and a protection film over the thin film transistor, the protection film including at least one of fluorinated polyimide, Teflon, cytop, fluoropolyarylether, Fluorinated parylene, PFCB, and BCB.

Abstract: A liquid crystal display unit includes a substrate; a gate electrode formed on the substrate; a gate insulating layer formed on the exposed surface of the substrate including the gate electrode; an intrinsic semiconductor layer and an impurity layer formed on the gate insulating layer; source and drain electrodes separately formed on the impurity semiconductor layer; an insulating layer formed on the source and drain electrodes, the insulating layer having a contact hole for exposing a channel region; and a pixel electrode formed on the insulating layer and connected to the drain electrode.