Abstract: A semiconductor device includes a back interlayer insulating film, a back wiring line disposed within the back interlayer insulating film, a fin-type pattern disposed on a first surface of the back wiring line, a source/drain pattern disposed on the fin-type pattern, and a back wiring contact connecting the back wiring line and source/drain pattern. A bottom surface of the source/drain pattern is connected to the fin-type pattern and faces the back wiring line. The back wiring contact includes a back contact barrier film, a back contact plug film, and a back ferroelectric material film. The back wiring contact includes a third surface facing the back wiring line. A vertical length from a second surface of the back wiring line to the third surface of the back wiring contact is less than a vertical length from the second surface to the bottom surface of the source/drain pattern.

Abstract: Disclosed are substrate processing apparatuses and substrate processing methods using the same. The substrate processing apparatus comprises a process chamber that provides a process space; a stage that supports a substrate, a gas spray device in the process space and upwardly spaced apart from the stage, a dielectric layer in the process space and upwardly spaced apart from the stage, a piezoelectric element that has a connection with and vibrates the dielectric layer, and a piezo power source that supplies the piezoelectric element with an alternating electric power.

Abstract: Integrated circuit devices may include two transistor stacks including lower transistors having different threshold voltages and upper transistors having different threshold voltages. Gate insulators of the lower transistors may have different dipole elements or different areal densities of dipole elements, and the upper transistors may have different gate electrode structures.

Abstract: Methods of forming a plurality of transistor stacks are provided. A method of forming a plurality of transistor stacks includes etching a plurality of nanosheets, using a plurality of spacers that are on sidewalls of a plurality of semiconductor fins as an etch mask, to provide a plurality of spaced-apart nanosheet stacks that each have at least one of the semiconductor fins thereon.

Abstract: The present invention is characterized by comprising: a plurality of user terminals for transmitting location information to a server; a photographing unit for capturing an image by means of a camera installed in a dash cam or a camera provided in the user terminal; an activation unit that activates an area where a preset update cycle has been exceeded as an area where information can be updated; an image transmission unit that, when location information of the user terminal received by the server is detected as the area activated by the activation unit, transmits the image captured by the photographing unit to the server through the user terminal; an image analysis unit that extracts map information including store information and terrain information from the image that the image transmission unit has transmitted to the server, and compares the map information with existing map information stored in the server to extract changed map information; and an updating unit that updates the existing map information

Abstract: Provided is a semiconductor device and method of manufacturing same.

Abstract: A multi-stack semiconductor device includes: a substrate; and a plurality of multi-stack transistor structures arranged on the substrate in a channel width direction, wherein the multi-stack transistor structure include at least one lower transistor structure and at least one upper transistor structure stacked above the lower transistor structure, wherein the lower and upper transistor structures include at least one channel layer as a current channel, wherein the lower transistor structures of at least two multi-stack transistor structures have different channel-layer widths.

Abstract: There is provided a semiconductor device capable of improving electrical characteristics and integration density. The semiconductor device includes an active pattern protruding from a substrate, the active pattern including long sidewalls extending in a first direction and opposite to each other in a second direction, a lower epitaxial pattern on the substrate and covering a part of the active pattern, a gate electrode on the lower epitaxial pattern and extending along the long sidewalls of the active pattern, and an upper epitaxial pattern on the active pattern and connected to an upper surface of the active pattern. The active pattern includes short sidewalls connecting with the long sidewalls of the active pattern, and at least one of the short sidewalls of the active pattern has a curved surface.

Abstract: Provided is a semiconductor architecture including a carrier substrate, a landing pad included in the carrier substrate, a first semiconductor device provided on a first surface of the carrier substrate, the first semiconductor device including a first component provided on the landing pad, and a second semiconductor device provided on a second surface of the carrier substrate, a second component protruding from the second semiconductor device being provided on the landing pad.

Abstract: There is provided a semiconductor device capable of improving electrical characteristics and integration density. The semiconductor device includes an active pattern protruding from a substrate, the active pattern including long sidewalls extending in a first direction and opposite to each other in a second direction, a lower epitaxial pattern on the substrate and covering a part of the active pattern, a gate electrode on the lower epitaxial pattern and extending along the long sidewalls of the active pattern, and an upper epitaxial pattern on the active pattern and connected to an upper surface of the active pattern. The active pattern includes short sidewalls connecting with the long sidewalls of the active pattern, and at least one of the short sidewalls of the active pattern has a curved surface.

Abstract: Provided is a semiconductor architecture including a carrier substrate, alignment marks provided in the carrier substrate, the alignment marks being provided from a first surface of the carrier substrate to a second surface of the carrier substrate, a first semiconductor device provided on the first surface of the carrier substrate based on the alignment marks, a second semiconductor device provided on the second surface of the carrier substrate based on the alignment marks and aligned with the first semiconductor device.

Abstract: A semiconductor device can include a field insulating film on a substrate and a fin-type pattern of a particular material, on the substrate, having a first sidewall and an opposing second sidewall. The fin-type pattern can include a first portion of the fin-type pattern that protrudes from an upper surface of the field insulating film and a second portion of the fin-type pattern disposed on the first portion. A third portion of the fin-type pattern can be disposed on the second portion where the third portion can be capped by a top rounded surface of the fin-type pattern and the first sidewall can have an undulated profile that spans the first, second and third portions.

Abstract: Integrated circuit devices may include two transistor stacks including lower transistors having different threshold voltages and upper transistors having different threshold voltages. Gate insulators of the lower transistors may have different dipole elements or different areal densities of dipole elements, and the upper transistors may have different gate electrode structures.

Abstract: A semiconductor device can include a field insulating film on a substrate and a fin-type pattern of a particular material, on the substrate, having a first sidewall and an opposing second sidewall. The fin-type pattern can include a first portion of the fin-type pattern that protrudes from an upper surface of the field insulating film and a second portion of the fin-type pattern disposed on the first portion. A third portion of the fin-type pattern can be disposed on the second portion where the third portion can be capped by a top rounded surface of the fin-type pattern and the first sidewall can have an undulated profile that spans the first, second and third portions.

Abstract: Provided is a portable power generating system including a base, an electric motor fixed on the base, a circular rotating table located at a center of the base and rotated by the electric motor, and two or more power generators fixed on the base and driven by the circular rotating table. Further, the system includes an extended generator shaft where magnet rollers are attached for increasing centripetal force and rotating on the rotating table in one direction. Also, a battery is provided for starting the system.

Abstract: Integrated circuit devices may include two transistor stacks including lower transistors having different threshold voltages and upper transistors having different threshold voltages. Gate insulators of the lower transistors may have different dipole elements or different areal densities of dipole elements, and the upper transistors may have different gate electrode structures.

Abstract: Nanosheet transistor devices are provided. A nanosheet transistor device includes a transistor stack that includes a lower nanosheet transistor having a first nanosheet width and a lower gate width. The transistor stack also includes an upper nanosheet transistor that is on the lower nanosheet transistor and that has a second nanosheet width and an upper gate width that are different from the first nanosheet width and the lower gate width, respectively. Related methods of forming a nanosheet transistor device are also provided.

Abstract: Provided is a semiconductor architecture including a carrier substrate, a landing pad included in the carrier substrate, a first semiconductor device provided on a first surface of the carrier substrate, the first semiconductor device including a first component provided on the landing pad, and a second semiconductor device provided on a second surface of the carrier substrate, a second component protruding from the second semiconductor device being provided on the landing pad.

Abstract: Nanosheet transistor devices are provided. A nanosheet transistor device includes a transistor stack that includes a lower nanosheet transistor having a first nanosheet width and a lower gate width. The transistor stack also includes an upper nanosheet transistor that is on the lower nanosheet transistor and that has a second nanosheet width and an upper gate width that are different from the first nanosheet width and the lower gate width, respectively. Related methods of forming a nanosheet transistor device are also provided.

Abstract: Provided is a renewable power generating system including a motor and one or more generators. Each of the motor and the generators comprises a front extended shaft and a rear extended shaft, a first flywheel is installed at the end of the rear extended shaft, and a second flywheel is installed at the end of the front extended shaft. Also, a third flywheel is detachably connected to the second flywheel, and a turbine installed on the third flywheel, and the turbine comprises multiple arms. The first flywheel, the second flywheel and the third flywheel rotates together when the motor rotates, and the system can produce an electric power when rotating.