Patents by Inventor Ki-Jae Song
Ki-Jae Song has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8872531Abstract: A semiconductor device and a test apparatus including the same, the semiconductor device including a command distributor receiving a serial command that is synchronized with a first clock signal and converting the serial command into a parallel command, a command decoder receiving the parallel command and generating a pattern sequence based on the parallel command, and a signal generator receiving the pattern sequence and generating operating signals synchronized with a second clock signal, wherein a frequency of the first clock signal is less than a frequency of the second clock signal.Type: GrantFiled: March 16, 2011Date of Patent: October 28, 2014Assignees: Samsung Electronics Co., Ltd., Postech Academy Industry FoundationInventors: Ki-jae Song, Ung-jin Jang, Jun-young Park, Sung-gu Lee, Hong-seok Yeon
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Patent number: 8832638Abstract: In a method of designing a printed circuit board, a package capacitance, a package inductance, and a chip capacitance of an actual memory device are calculated. A signal line capacitance and a signal line inductance per unit length of a signal line are calculated based on characteristics of the printed circuit board. A length of the signal line for each pin is determined based on the package capacitance and the signal line capacitance.Type: GrantFiled: February 28, 2013Date of Patent: September 9, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-Hoon Jeong, Chang-Woo Ko, Ki-Jae Song, Hun-Kyo Seo
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Patent number: 8750061Abstract: A memory test system is disclosed. The memory system includes a memory device, a tester generating a clock signal and a test signal for testing the memory device, and an optical splitting module. The optical splitting module comprises an electrical-optical signal converting unit which converts each of the clock signal and the test signal into an optical signal to output the clock signal and the test signal as an optical clock signal and an optical test signal. The optical splitting unit further comprises an optical signal splitting unit which splits each of the optical clock signal and the optical test signal into n signals (n being at least two), and an optical-electrical signal converting unit which receives the split optical clock signal and the split optical test signal to convert the split optical clock signal and the split optical test signal into electrical signals used in the memory device.Type: GrantFiled: September 16, 2011Date of Patent: June 10, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Soo-Haeng Cho, Ki-jae Song, Sung-dong Suh, Kyoung-ho Ha, Seong-gu Kim, Yeoung-kum Kim, In-sung Joe
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Publication number: 20130342236Abstract: A test interface board comprises at least one switch matrix including a plurality of switching elements that connect a plurality of connection nodes to each other. The at least one switch matrix is configured to connect a plurality of channels of an automatic test equipment (ATE) to respective pin positions corresponding to a device under test (DUT) in response to switching control signals. The plurality of channels provide test operation signals for testing the DUT. A control logic is configured to generate the switching control signals based on pin configuration information of the DUT.Type: ApplicationFiled: March 14, 2013Publication date: December 26, 2013Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ki-Jae Song, Jong-Woon Yoo, Sang-Kyeong Han, Gil-Beag Kim
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Patent number: 8482308Abstract: A connecting unit to test a semiconductor chip and an apparatus to test the semiconductor chip having the same include a plurality of connectors, on which a semiconductor chip having a certain pattern of electrical connection terminals, having a plurality of holes, cables configured to electrically connect the electrical connection terminals to the exterior, and coupling units configured to selectively electrically connect the cables to the electrical connection terminals through the holes. Therefore, it is possible to perform electrical tests of semiconductor chips having various patterns of electrical connection terminals and receive the semiconductor chips in a tray at a time.Type: GrantFiled: November 9, 2009Date of Patent: July 9, 2013Assignee: Samsung Electronics Co., LtdInventors: Ki-Jae Song, Hun-Kyo Seo, Jae-Il Lee, Jong-Won Han, Jong-Pil Park
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Patent number: 8407659Abstract: In a method of designing a printed circuit board, a package capacitance, a package inductance, and a chip capacitance of an actual memory device are calculated. A signal line capacitance and a signal line inductance per unit length of a signal line are calculated based on characteristics of the printed circuit board. A length of the signal line for each pin is determined based on the package capacitance and the signal line capacitance.Type: GrantFiled: July 2, 2010Date of Patent: March 26, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-Hoon Jeong, Chang-Woo Ko, Ki-Jae Song, Hun-Kyo Seo
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Publication number: 20120152603Abstract: A printed circuit board (PCB) for transmitting a signal that includes a first layer, and a second layer disposed on the first layer. The first layer includes a first signal line to transmit the signal, and a first ground line and a second ground line disposed at both sides of the first signal line to be apart from the first signal line by a first distance. The second layer includes a second signal line to transmit the signal, and a third ground line and a fourth ground line disposed at both sides of the second signal line to be apart from the second signal line by a second distance. The third ground line or the fourth ground line is disposed on the first signal line.Type: ApplicationFiled: December 8, 2011Publication date: June 21, 2012Applicant: Samsung Electronics Co., Ltd.Inventors: Ki Jae SONG, Woo Ik Park
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Publication number: 20120150478Abstract: In a method of testing an object, a first test pattern for testing a first device in the object may be set in a tester. A second test pattern for testing a second device in the object may be set in a test head electrically connected between the tester and the object. The first test pattern may be provided to the first device through the test head and the second test pattern may be provided to the second device by the test head to simultaneously test the first device and the second device. Thus, the first device and the second device different from each other may be simultaneously tested without changing test conditions in the tester, so that a time for testing the object may be reduced.Type: ApplicationFiled: December 14, 2011Publication date: June 14, 2012Inventors: Ki-Jae Song, Sung-Soo Lee
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Patent number: 8106675Abstract: A test system may include a test device, a switching unit and/or a test board. The test device may be configured to generate a first test signal swinging between a first voltage level and a second voltage level, and the first voltage level may be lower than the second voltage level. The switching unit may be coupled to the test device, and configured to switch the first test signal to provide a second test signal swinging between a third voltage level and a fourth voltage level. The third voltage level may be lower than the fourth voltage level. A plurality of devices under test (DUTs) may be mounted on the test board. Each of the plurality of DUTs may be connected in parallel with respect to one another to the switching unit through a transmission line.Type: GrantFiled: June 29, 2009Date of Patent: January 31, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Ki-Jae Song, Hun-Kyo Seo
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Publication number: 20120002495Abstract: A memory test system is disclosed. The memory system includes a memory device, a tester generating a clock signal and a test signal for testing the memory device, and an optical splitting module. The optical splitting module comprises an electrical-optical signal converting unit which converts each of the clock signal and the test signal into an optical signal to output the clock signal and the test signal as an optical clock signal and an optical test signal. The optical splitting unit further comprises an optical signal splitting unit which splits each of the optical clock signal and the optical test signal into n signals (n being at least two), and an optical-electrical signal converting unit which receives the split optical clock signal and the split optical test signal to convert the split optical clock signal and the split optical test signal into electrical signals used in the memory device.Type: ApplicationFiled: September 16, 2011Publication date: January 5, 2012Inventors: Soo-Haeng Cho, Ki-jae Song, Sung-dong Suh, Kyoung-ho Ha, Seong-gu Kim, Yeoung-kum Kim, In-sung Joe
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Publication number: 20110227593Abstract: A semiconductor device and a test apparatus including the same, the semiconductor device including a command distributor receiving a serial command that is synchronized with a first clock signal and converting the serial command into a parallel command, a command decoder receiving the parallel command and generating a pattern sequence based on the parallel command, and a signal generator receiving the pattern sequence and generating operating signals synchronized with a second clock signal, wherein a frequency of the first clock signal is less than a frequency of the second clock signal.Type: ApplicationFiled: March 16, 2011Publication date: September 22, 2011Inventors: Ki-jae SONG, Ung-jin JANG, Jun-young PARK, Sung-gu LEE, Hong-seok YEON
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Patent number: 8023349Abstract: A memory test system is disclosed. The memory system includes a memory device, a tester generating a clock signal and a test signal for testing the memory device, and an optical splitting module. The optical splitting module comprises an electrical-optical signal converting unit which converts each of the clock signal and the test signal into an optical signal to output the clock signal and the test signal as an optical clock signal and an optical test signal. The optical splitting unit further comprises an optical signal splitting unit which splits each of the optical clock signal and the optical test signal into n signals (n being at least two), and an optical-electrical signal converting unit which receives the split optical clock signal and the split optical test signal to convert the split optical clock signal and the split optical test signal into electrical signals used in the memory device.Type: GrantFiled: January 20, 2010Date of Patent: September 20, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Soo-Haeng Cho, Ki-jae Song, Sung-dong Suh, Kyoung-ho Ha, Seong-gu Kim, Yeoung-kum Kim, In-sung Joe
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Publication number: 20110004861Abstract: In a method of designing a printed circuit board, a package capacitance, a package inductance, and a chip capacitance of an actual memory device are calculated. A signal line capacitance and a signal line inductance per unit length of a signal line are calculated based on characteristics of the printed circuit board. A length of the signal line for each pin is determined based on the package capacitance and the signal line capacitance.Type: ApplicationFiled: July 2, 2010Publication date: January 6, 2011Inventors: Jae-Hoon Jeong, Chang-Woo Ko, Ki-Jae Song, Hun-Kyo Seo
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Publication number: 20100194399Abstract: A memory test system is disclosed. The memory system includes a memory device, a tester generating a clock signal and a test signal for testing the memory device, and an optical splitting module. The optical splitting module comprises an electrical-optical signal converting unit which converts each of the clock signal and the test signal into an optical signal to output the clock signal and the test signal as an optical clock signal and an optical test signal. The optical splitting unit further comprises an optical signal splitting unit which splits each of the optical clock signal and the optical test signal into n signals (n being at least two), and an optical-electrical signal converting unit which receives the split optical clock signal and the split optical test signal to convert the split optical clock signal and the split optical test signal into electrical signals used in the memory device.Type: ApplicationFiled: January 20, 2010Publication date: August 5, 2010Inventors: Soo-Haeng Cho, Ki-Jae Song, Sung-dong Suh, Kyoung-ho Ha, Seong-gu Kim, Yeoung-Kum Kim, In-sung Joe
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Patent number: 7755449Abstract: A printed circuit board (PCB) including an impedance-matched strip transmission line includes a strip transmission line including a main line and at least one pair of branch lines branching off from the main line. An upper ground layer is disposed over the strip transmission line and has upper opening parts corresponding in position to the branch lines. A lower ground layer is disposed under the strip transmission line and has lower opening parts corresponding in position to the branch lines. The upper and lower opening parts are symmetric about the branch lines of the strip transmission line.Type: GrantFiled: July 3, 2008Date of Patent: July 13, 2010Assignee: Samsung Electronics Co., Ltd.Inventor: Ki-Jae Song
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Publication number: 20100117670Abstract: A connecting unit to test a semiconductor chip and an apparatus to test the semiconductor chip having the same include a plurality of connectors, on which a semiconductor chip having a certain pattern of electrical connection terminals, having a plurality of holes, cables configured to electrically connect the electrical connection terminals to the exterior, and coupling units configured to selectively electrically connect the cables to the electrical connection terminals through the holes. Therefore, it is possible to perform electrical tests of semiconductor chips having various patterns of electrical connection terminals and receive the semiconductor chips in a tray at a time.Type: ApplicationFiled: November 9, 2009Publication date: May 13, 2010Applicant: Samsung Electronics Co., Ltd.Inventors: Ki-jae SONG, Hun-Kyo SEO, Jae-Il LEE, Jong-Won HAN, Jong-Pil PARK
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Patent number: 7671617Abstract: A test system includes: a tester; and a test board, on which a multi-chip package including plural memories is mounted, being connected to the tester by way of a transmission line. The transmission line includes a compensation unit for compensating signal distortion.Type: GrantFiled: November 7, 2007Date of Patent: March 2, 2010Assignee: Samsung Electronics Co., Ltd.Inventor: Ki-Jae Song
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Publication number: 20090322369Abstract: A test system may include a test device, a switching unit and/or a test board. The test device may be configured to generate a first test signal swinging between a first voltage level and a second voltage level, and the first voltage level may be lower than the second voltage level. The switching unit may be coupled to the test device, and configured to switch the first test signal to provide a second test signal swinging between a third voltage level and a fourth voltage level. The third voltage level may be lower than the fourth voltage level. A plurality of devices under test (DUTs) may be mounted on the test board. Each of the plurality of DUTs may be connected in parallel with respect to one another to the switching unit through a transmission line.Type: ApplicationFiled: June 29, 2009Publication date: December 31, 2009Inventors: Ki-Jae Song, Hun-Kyo Seo
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Publication number: 20090009261Abstract: A printed circuit board (PCB) including an impedance-matched strip transmission line includes a strip transmission line including a main line and at least one pair of branch lines branching off from the main line. An upper ground layer is disposed over the strip transmission line and has upper opening parts corresponding in position to the branch lines. A lower ground layer is disposed under the strip transmission line and has lower opening parts corresponding in position to the branch lines. The upper and lower opening parts are symmetric about the branch lines of the strip transmission line.Type: ApplicationFiled: July 3, 2008Publication date: January 8, 2009Applicant: Samsung Electronics Co., Ltd.Inventor: Ki-Jae Song
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Publication number: 20080150097Abstract: Provided are a semiconductor device with reduced power noise, which can be used in a high-speed device with an operating frequency of at or above about 1 GHz and does not have any spatial restriction due to signal patterns or other structures. The semiconductor device includes a power panel, an insulating layer, and a stub unit. The power panel has electrical devices formed thereon. The insulating layer covers the power panel. The stub unit is formed on the insulating layer and has one or more fan-shaped stubs electrically connected to the power panel through a via contact penetrating the insulating layer.Type: ApplicationFiled: September 6, 2007Publication date: June 26, 2008Applicant: Samsung Electronics, Co., Ltd.Inventor: Ki-Jae Song