Patents by Inventor Ki-joon Kim

Ki-joon Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10403876
    Abstract: Disclosed are an electrode lead connecting structure capable of simplifying an assembly process of busbars by integrating sensing and electrode busbars, and of minimizing worker's mistakes during the assembly process by almost horizontally arranging busbars on a printed circuit board for each level, a battery module including the electrode lead connecting structure, and a battery pack including the battery module. An electrode lead connecting structure according to the present disclosure includes a printed circuit board, first and second electrode-integrated sensing busbars provided at a lowest level of one side edge of the printed circuit board and at a highest level of an opposite side edge of the printed circuit board, respectively, a first sensing busbar group located on the first L-shaped end strip busbar at the one side edge, and a second sensing busbar group located under the second L-shaped end strip busbar at the opposite side edge.
    Type: Grant
    Filed: July 11, 2016
    Date of Patent: September 3, 2019
    Assignee: LG CHEM, LTD.
    Inventors: Yong-Joon Choi, Ki-Youn Kim, Duck-Hee Moon, Jun-Yeob Seong, Sung-Chun Yu, Gang-U Lee, Jung-Hang Lee, Sang-Yoon Jeong
  • Publication number: 20190259910
    Abstract: Disclosed in one embodiment is a semiconductor device comprising: a light-emitting structure including a first conductive semiconductor layer, a second conductive semiconductor layer, and an active layer arranged between the first conductive semiconductor layer and the second conductive semiconductor layer; a first electrode electrically connected with the first conductive semiconductor layer; a second electrode electrically connected with the second conductive semiconductor layer; a reflective layer arranged on the second electrode; and a capping layer arranged on the reflective layer and including a plurality of layers, wherein the capping layer includes a first layer directly arranged on the reflective layer and the first layer includes Ti.
    Type: Application
    Filed: November 3, 2017
    Publication date: August 22, 2019
    Inventors: Youn Joon SUNG, Ki Man KANG, Min Sung KIM, Su lk PARK, Yong Gyeong LEE, Eun Dk LEE, Hyun Soo LIM
  • Publication number: 20190239098
    Abstract: A device for performing wireless communication at least one processor configured to generate a condition signal based on at least one parameter associated with the device or the wireless communication, and select at least one of a plurality of signal processing algorithms for performing at least one of a plurality of signal processing functions based on the condition signal, each of the plurality of signal processing functions being associated with the wireless communication.
    Type: Application
    Filed: January 16, 2019
    Publication date: August 1, 2019
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jun-ho Lee, In-yup Kang, Young-seok Jung, Min-goo Kim, In-hyoung Kim, Ki-joon Hong
  • Patent number: 10367137
    Abstract: Disclosed are an electronic device comprising a semiconductor memory. The semiconductor memory includes a variable resistance element including a free layer having a variable magnetization direction; a pinned layer having a fixed magnetization direction; and a tunnel barrier layer interposed between the free layer and the pinned layer, wherein the free layer includes: a first free layer adjacent to the tunnel barrier layer and having a perpendicular magnetic anisotropy at an interface with the tunnel barrier layer; and a second free layer spaced apart from the tunnel barrier layer by the first free layer and having a saturation magnetization lower than a saturation magnetization of the first free layer.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: July 30, 2019
    Assignee: SK hynix Inc.
    Inventors: Guk-Cheon Kim, Ki-Seon Park, Bo-Mi Lee, Won-Joon Choi, Yang-Kon Kim
  • Publication number: 20190196533
    Abstract: A modem chip includes a processor configured to generate instructions, a timing controller configured to respectively generate control signals corresponding to the instructions at the execution times of the instructions, and a plurality of intellectual property blocks, each configured to operate in response to a corresponding control signal of the control signals. The timing controller includes a heap sorting circuit configured to sort the instructions according to execution orders of the instructions based on heap sorting using the execution times, a reference counter configured to generate a reference time, and a signal generator configured to generate a control signal corresponding to a current instruction when the reference time matches the execution time of the current instruction having a highest execution order among the instructions.
    Type: Application
    Filed: December 24, 2018
    Publication date: June 27, 2019
    Inventors: Kyung-Min Kim, Won-Seok Jeong, IL-Muk Choi, Jun-Ho Lee, Sung-Chul Han, Ki-Joon Hong, Seung-Joong Hwang
  • Publication number: 20190162365
    Abstract: The present disclosure relates to a pressure vessel equipped with a permeated gas discharging structure, the pressure vessel including a nozzle boss into and from which a gas flows and is discharged; a liner coupled to a flange portion of the nozzle boss and provided with a space formed therein for receiving fluid; a discharge path forming part configured to form a gas discharging path from the nozzle boss side along an outer surface of the liner in a central axial direction; and a composite material provided at outer sides of the liner and the discharge path forming part
    Type: Application
    Filed: April 5, 2017
    Publication date: May 30, 2019
    Applicants: Hyundai Motor Company, KIA Motors Corporation
    Inventors: Jae Han CHUNG, Hyun Joon LEE, Ki Ho HWANG, Gye Hyoung YOO, Seok Bong HEO, Jong Lyul Kim
  • Patent number: 10305030
    Abstract: Electronic devices and systems having semiconductor memory are provided. In one implementation, for example, an electronic device may include a substrate; an under layer disposed over the substrate and including conductive hafnium silicate; a free layer disposed over the under layer and having a variable magnetization direction; a tunnel barrier layer disposed over the free layer; and a pinned layer disposed over the tunnel barrier layer and having a pinned magnetization direction, and wherein the free layer includes: a first ferromagnetic material; a second ferromagnetic material having a coercive force smaller than that of the first ferromagnetic material; and an amorphous spacer interposed between the first ferromagnetic material and the second ferromagnetic material.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: May 28, 2019
    Assignee: SK hynix Inc.
    Inventors: Won-Joon Choi, Ki-Seon Park, Cha-Deok Dong, Bo-Mi Lee, Guk-Cheon Kim, Seung-Mo Noh, Min-Suk Lee, Chan-Sik Park, Jae-Heon Kim, Choi-Dong Kim, Jae-Hong Kim, Yang-Kon Kim, Jong-Koo Lim, Jeong-Myeong Kim
  • Patent number: 10305946
    Abstract: Disclosed is a method and apparatus for providing a group call service using mobile voice over Internet protocol (mVolP). According to one embodiment, an interface is provided to transmit a request signal for a group call to members of a group chat room, and from among the group chat room members, it may be determined which members are able to participate in a group call as group call members. A new group call chat room may be created and include the group call members. The request signal may be transmitted in the created new group call chat room.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: May 28, 2019
    Assignee: KAKAO CORP.
    Inventors: Young Joon Ryu, Hyang Deok Yim, Choon Taek Kim, Jung Taek Kim, Se Jong Seo, Dae Gil Kim, Dong Kuk Woo, Seok Kyoo Lee, Ki Yong Sim, Jun Jae Kim, Chang Ho Park, Hyun Seok Hwang, Seong Hark Kang
  • Patent number: 10294360
    Abstract: A polypropylene resin composition includes a base resin, a thermoplastic elastomer, and an inorganic filler. The base resin is a polypropylene-based mixed resin including a first resin, a second resin, a third resin, and a fourth resin. The first resin is a homopolypropylene resin. The second resin, the third resin, and the fourth resin are each a polypropylene-based block copolymer resin. A melt index of the second resin measured at a temperature of 230° C. and under a load of 2.16 kg is higher than a melt index of each of the third resin and the fourth resin measured under the same condition. A flexural modulus of the third resin measured in accordance with ASTM D790 is lower than a flexural modulus of the fourth resin measured under the same condition.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: May 21, 2019
    Assignees: Hyundai Motor Company, Kia Motors Corporation, LG Hausys, Ltd., Hyundai EP Co., Ltd.
    Inventors: Hyun Gyung Kim, Hee Joon Lee, Eun Seob Shin, Hyeok Lee, Ki Hyun Sung, Chun Ho Park
  • Patent number: 10297801
    Abstract: The present disclosure relates to a battery pack having improved assemblability, processability, and productivity, and configured to reduce manufacturing costs and enhance the scalability and durability of a pack case. The battery pack includes: a cell assembly including a plurality of secondary cells and a plurality of cartridges, the cartridges being configured to be stacked on one another and to accommodate the secondary cells while surrounding outer circumferential portions of the secondary cells from outsides of the secondary cells; a lower housing having an empty inner space to accommodate the cell assembly in the inner space, the lower housing being opened on an upper side thereof; a lower end plate including a plate-shaped metallic material and placed in surface contact with a lower surface of the lower housing; and a lower cover placed on a lower portion of the lower end plate to cover the lower end plate, the lower cover being fixedly coupled to the lower housing.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: May 21, 2019
    Assignee: LG CHEM, LTD.
    Inventors: Ki-Youn Kim, Duck-Hee Moon, Jun-Yeob Seong, Sung-Chun Yu, Gang-U Lee, Jung-Hang Lee, Sang-Yoon Jeong, Yong-Joon Choi
  • Patent number: 10029771
    Abstract: Disclosed herein is a floating recovery device for underwater equipment. The device includes a recovery body partitioned into a first compartment, a second compartment, and a third compartment by a partition wall, first and second pressure tanks installed in the first and second compartments, respectively, first and second striking parts fastened to the first and second pressure tanks, respectively, to strike the first and second pressure tanks, first and second actuators wirelessly actuating the first and second striking parts, respectively, and a buoyancy generator installed in the third compartment, and inflated by high-pressure gas introduced from the first and second pressure tanks, thus generating buoyancy. Such a configuration allows the pressure tank to be wirelessly struck for the purpose of supplying high-pressure gas to the buoyancy generator and floating the underwater equipment in the event of the loss of the underwater equipment.
    Type: Grant
    Filed: March 14, 2017
    Date of Patent: July 24, 2018
    Inventor: Ki Joon Kim
  • Publication number: 20180118313
    Abstract: Disclosed herein is a floating recovery device for underwater equipment. The device includes a recovery body partitioned into a first compartment, a second compartment, and a third compartment by a partition wall, first and second pressure tanks installed in the first and second compartments, respectively, first and second striking parts fastened to the first and second pressure tanks, respectively, to strike the first and second pressure tanks, first and second actuators wirelessly actuating the first and second striking parts, respectively, and a buoyancy generator installed in the third compartment, and inflated by high-pressure gas introduced from the first and second pressure tanks, thus generating buoyancy. Such a configuration allows the pressure tank to be wirelessly struck for the purpose of supplying high-pressure gas to the buoyancy generator and floating the underwater equipment in the event of the loss of the underwater equipment.
    Type: Application
    Filed: March 14, 2017
    Publication date: May 3, 2018
    Inventor: Ki Joon KIM
  • Patent number: 9754817
    Abstract: A semiconductor device and methods of forming a semiconductor device are disclosed. In the methods, a layer, such as an insulating interlayer, is formed on a substrate. A first trench is formed in the layer, and a mask layer is formed in the first trench. The mask layer has a first thickness from a bottom surface of the first trench to the top of the mask layer. The mask layer is patterned to form a mask that at least partially exposes a sidewall of the first trench. A portion of the mask adjacent to the exposed sidewall of the first trench has a second thickness smaller than the first thickness. The layer is etched to form a second trench using the mask as an etching mask. The second trench is in fluid communication with the first trench. A conductive pattern is formed in the first trench and the second trench.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: September 5, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kil-Ho Lee, Se-Woong Park, Ki-Joon Kim
  • Publication number: 20160329236
    Abstract: A semiconductor device and methods of forming a semiconductor device are disclosed. In the methods, a layer, such as an insulating interlayer, is formed on a substrate. A first trench is formed in the layer, and a mask layer is formed in the first trench. The mask layer has a first thickness from a bottom surface of the first trench to the top of the mask layer. The mask layer is patterned to form a mask that at least partially exposes a sidewall of the first trench. A portion of the mask adjacent to the exposed sidewall of the first trench has a second thickness smaller than the first thickness. The layer is etched to form a second trench using the mask as an etching mask. The second trench is in fluid communication with the first trench. A conductive pattern is formed in the first trench and the second trench.
    Type: Application
    Filed: June 1, 2016
    Publication date: November 10, 2016
    Inventors: Kil-Ho LEE, Se-Woong PARK, Ki-Joon KIM
  • Patent number: 9379003
    Abstract: A semiconductor device and methods of forming a semiconductor device are disclosed. In the methods, a layer, such as an insulating interlayer, is formed on a substrate. A first trench is formed in the layer, and a mask layer is formed in the first trench. The mask layer has a first thickness from a bottom surface of the first trench to the top of the mask layer. The mask layer is patterned to form a mask that at least partially exposes a sidewall of the first trench. A portion of the mask adjacent to the exposed sidewall of the first trench has a second thickness smaller than the first thickness. The layer is etched to form a second trench using the mask as an etching mask. The second trench is in fluid communication with the first trench. A conductive pattern is formed in the first trench and the second trench.
    Type: Grant
    Filed: October 15, 2013
    Date of Patent: June 28, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kil-Ho Lee, Se-Woong Park, Ki-Joon Kim
  • Patent number: 9356071
    Abstract: An insulation layer is formed on a substrate. A first mask is formed on the insulation layer. The first mask includes a plurality of line patterns arranged in a second direction. The plurality of line patterns extend in a first direction substantially perpendicular to the second direction. A second mask is formed on the insulation layer and the first mask. The second mask includes an opening partially exposing the plurality of line patterns. The opening has an uneven boundary at one of a first end portion in the first direction and a second end portion in a third direction substantially opposite to the first direction. The insulation layer is partially removed using the first mask and the second mask as an etching mask, thereby forming a plurality of first trenches and second trenches. The plurality of first trenches and the second trenches are arranged in a staggered pattern.
    Type: Grant
    Filed: July 20, 2015
    Date of Patent: May 31, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Bum-Seok Seo, Ki-Joon Kim, Kil-Ho Lee
  • Patent number: 9246083
    Abstract: Memory devices and methods of fabricating the same include a substrate including a cell region and a peripheral circuit region, data storages on the cell region, first bit lines on and coupled to the data storages, first contacts coupled to peripheral transistors on the peripheral circuit region, and second bit lines on and coupled to the first contacts. The second bit lines may each have a lowermost surface lower than a lowermost surface of the data storages.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: January 26, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kilho Lee, Ki Joon Kim, Se Woong Park
  • Publication number: 20150325625
    Abstract: An insulation layer is formed on a substrate. A first mask is formed on the insulation layer. The first mask includes a plurality of line patterns arranged in a second direction. The plurality of line patterns extend in a first direction substantially perpendicular to the second direction. A second mask is formed on the insulation layer and the first mask. The second mask includes an opening partially exposing the plurality of line patterns. The opening has an uneven boundary at one of a first end portion in the first direction and a second end portion in a third direction substantially opposite to the first direction. The insulation layer is partially removed using the first mask and the second mask as an etching mask, thereby forming a plurality of first trenches and second trenches. The plurality of first trenches and the second trenches are arranged in a staggered pattern.
    Type: Application
    Filed: July 20, 2015
    Publication date: November 12, 2015
    Inventors: Bum-Seok SEO, Ki-Joon KIM, Kil-Ho LEE
  • Patent number: 9118002
    Abstract: An insulation layer is formed on a substrate. A first mask is formed on the insulation layer. The first mask includes a plurality of line patterns arranged in a second direction. The plurality of line patterns extend in a first direction substantially perpendicular to the second direction. A second mask is formed on the insulation layer and the first mask. The second mask includes an opening partially exposing the plurality of line patterns. The opening has an uneven boundary at one of a first end portion in the first direction and a second end portion in a third direction substantially opposite to the first direction. The insulation layer is partially removed using the first mask and the second mask as an etching mask, thereby forming a plurality of first trenches and second trenches. The plurality of first trenches and the second trenches are arranged in a staggered pattern.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: August 25, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Bum-Seok Seo, Ki-Joon Kim, Kil-Ho Lee
  • Patent number: 9087871
    Abstract: Nonvolatile memory devices and methods of fabricating the same, include, forming a transistor in a first region of a substrate, forming a contact which is connected to the transistor, forming an information storage portion, which is disposed two-dimensionally, in a second region of the substrate, sequentially forming a stop film and an interlayer insulating film which cover the contact and the information storage portion, forming a first trench, which exposes the stop film, on the contact, and forming a second trench which extends through the stop film to expose the contact, wherein a bottom surface of the first trench is lower than a bottom surface of the information storage portion.
    Type: Grant
    Filed: July 19, 2013
    Date of Patent: July 21, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kil-Ho Lee, Ki-Joon Kim, Se-Woong Park