Patents by Inventor Ki Jun Nam
Ki Jun Nam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11914451Abstract: Apparatuses and methods for providing internal power voltages are described. An example apparatus includes a first, second, and third clamp circuits, and a clamp control circuit. The first clamp circuit is configured to receive a first external power voltage and provide a first voltage drop to provide a first internal power voltage. The second clamp circuit is configured to receive the first external power voltage and provide a second voltage drop to provide a second internal power voltage, wherein the first voltage drop is greater than the second voltage drop. The third clamp circuit is configured to receive a second external power voltage and provide the second external power voltage as the second internal power voltage when the second external power voltage is activated. The clamp control circuit is configured to activate the third clamp circuit when the second external power voltage reaches a trigger voltage level.Type: GrantFiled: August 23, 2022Date of Patent: February 27, 2024Assignee: Micron Technology, Inc.Inventors: Ki-Jun Nam, Younghoon Oh
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Publication number: 20240055044Abstract: A memory device includes a memory cell that stores data. The memory device also includes a pair of digit lines that carry the data from the memory cell. The memory device further includes a sense amplifier that senses and amplifies voltages received at the pair of digit lines. The memory device also includes a replica sense amplifier that generates a replica common mode voltage associated with a common mode voltage of the pair of digit lines.Type: ApplicationFiled: August 9, 2022Publication date: February 15, 2024Inventor: Ki-Jun Nam
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Publication number: 20230393645Abstract: Apparatuses and methods for providing internal power voltages are described. An example apparatus includes a first, second, and third clamp circuits, and a clamp control circuit. The first clamp circuit is configured to receive a first external power voltage and provide a first voltage drop to provide a first internal power voltage. The second clamp circuit is configured to receive the first external power voltage and provide a second voltage drop to provide a second internal power voltage, wherein the first voltage drop is greater than the second voltage drop. The third clamp circuit is configured to receive a second external power voltage and provide the second external power voltage as the second internal power voltage when the second external power voltage is activated. The clamp control circuit is configured to activate the third clamp circuit when the second external power voltage reaches a trigger voltage level.Type: ApplicationFiled: August 23, 2022Publication date: December 7, 2023Applicant: MICRON TECHNOLOGY, INC.Inventors: Ki-Jun Nam, Younghoon Oh
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Patent number: 11798634Abstract: Methods, systems, and devices for sequential voltage control for a memory device are described. A memory device may have various voltage sources that support different voltage levels used in various operations of the memory device. Voltage sources of a memory device may be disabled under some circumstances, such as when the memory device is idled, or operated in a low-power or powered-down mode, among other circumstances. In accordance with examples as disclosed herein, voltage sources of a memory device or memory die may be sequentially enabled or sequentially disabled. For example, voltage sources may be enabled in an order from voltage sources having relatively higher nominal voltages to voltage sources having relatively lower voltages, or disabled in an order from voltage sources having relatively lower nominal voltages to voltage sources having relatively higher voltages.Type: GrantFiled: February 18, 2022Date of Patent: October 24, 2023Assignee: Micron Technology, Inc.Inventors: Ki-Jun Nam, Takamasa Suzuki, Yantao Ma, Yasushi Matsubara
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Publication number: 20230178139Abstract: A system (100) for providing a timing signal with tunable temperature dependency in an electronic device may include a timing circuit (102) and an initial setting circuit (104). The timing circuit (102) may include a delay stage (106) and a gate stage (108). The delay stage (106) may be configured to receive an input signal and to produce a delayed signal by introducing a delay to the input signal. The gate stage (108) may be configured to receive the delayed signal and a threshold setting signal, to produce an output signal using the delayed signal and a logic threshold, and to set an initial value of the logic threshold according to the threshold setting signal. The initial setting circuit (104) may be configured to allow the threshold setting signal to be tuned for providing the time delay with a specified temperature dependency.Type: ApplicationFiled: May 29, 2020Publication date: June 8, 2023Inventors: Si Hong Kim, Ki-Jun Nam, Zhi Qi Huang, John David Porter
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Patent number: 11656645Abstract: An electronic device may include a main circuit including multiple sub-circuits powered by a direct-current (DC) power supply circuit. The main circuit has a main circuit current demand being a time-varying demand for a DC voltage-regulated supply current being a function of a number of the sub-circuits being active. The DC power supply circuit may include multiple DC voltage regulators to provide the main circuit with the supply current and a command decoding and power management circuit to control enablement of the voltage regulators. The command decoding and power management circuit may be configured to detect an instant value of the main circuit current demand and to selectively enable one or more of the voltage regulators based on the detected instant value.Type: GrantFiled: January 7, 2022Date of Patent: May 23, 2023Assignee: Micron Technology, Inc.Inventors: Si Hong Kim, Ki-Jun Nam
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Patent number: 11658662Abstract: Methods, systems, and devices for leakage current reduction in electronic devices are described. Electronic devices may be susceptible to leakage currents when operating in a first mode, such as an inactive (e.g., a standby) mode. To mitigate leakage current, an electronic device may include transistors coupled in cascode configuration where a gate of a drain-side transistor in the cascode configuration is configured to be biased by an adjustable (e.g., a dynamic) control signal. When the transistors are inactive (e.g., “off”), the control signal may be adjusted to prevent leakage associated with the inactive transistors. Further, a source-side transistor in the cascode configuration may be configured to have a high threshold voltage (e.g., relative to the drain-side transistor).Type: GrantFiled: October 23, 2020Date of Patent: May 23, 2023Assignee: Micron Technology, Inc.Inventors: Hiroshi Akamatsu, Ki-Jun Nam, John David Porter
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Publication number: 20230109187Abstract: Methods, systems, and devices for grouping power supplies for a power saving mode are described to configure a memory device with groups of internal power supplies whose voltage levels may be successively modified according to a group order signaled by an on-die timer. For example, when the memory device enters a deep sleep mode, respective voltage levels of a first group of internal power supplies may be modified to respective external power supply voltage levels at a first time, respective voltage levels of a second group of internal power supplies may be modified to respective external power supply voltage levels at a second time, and so on. When the memory device exits the deep sleep mode, the groups of internal voltage supplies may be modified from the respective external power supply voltage levels to respective operational voltage levels in a group order that is opposite to the entry group order.Type: ApplicationFiled: October 5, 2022Publication date: April 6, 2023Inventors: Ki-Jun Nam, Yantao Ma, Yasushi Matsubara, Takamasa Suzuki
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Patent number: 11615828Abstract: Apparatuses and methods related to power domain boundary protection in memory. A number of embodiments can include using a voltage detector to monitor a floating power supply voltage used to power a number of logic components while a memory device operates in a reduced power mode, and responsive to the voltage detector detecting that the floating power supply voltage reaches a threshold value while the memory device is in the reduced power mode, providing a control signal to protection logic to prevent a floating output signal driven from one or more of the logic components from being provided across a power domain boundary to one or more of a different number of logic components.Type: GrantFiled: November 11, 2021Date of Patent: March 28, 2023Assignee: Micron Technology, Inc.Inventors: Ki-Jun Nam, Hiroshi Akamatsu, Takamasa Suzuki, Yasushi Matsubara
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Patent number: 11487346Abstract: Methods, systems, and devices for grouping power supplies for a power saving mode are described to configure a memory device with groups of internal power supplies whose voltage levels may be successively modified according to a group order signaled by an on-die timer. For example, when the memory device enters a deep sleep mode, respective voltage levels of a first group of internal power supplies may be modified to respective external power supply voltage levels at a first time, respective voltage levels of a second group of internal power supplies may be modified to respective external power supply voltage levels at a second time, and so on. When the memory device exits the deep sleep mode, the groups of internal voltage supplies may be modified from the respective external power supply voltage levels to respective operational voltage levels in a group order that is opposite to the entry group order.Type: GrantFiled: June 2, 2020Date of Patent: November 1, 2022Assignee: Micron Technogy, Inc.Inventors: Ki-Jun Nam, Yantao Ma, Yasushi Matsubara, Takamasa Suzuki
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Publication number: 20220246219Abstract: Methods, systems, and devices for sequential voltage control for a memory device are described. A memory device may have various voltage sources that support different voltage levels used in various operations of the memory device. Voltage sources of a memory device may be disabled under some circumstances, such as when the memory device is idled, or operated in a low-power or powered-down mode, among other circumstances. In accordance with examples as disclosed herein, voltage sources of a memory device or memory die may be sequentially enabled or sequentially disabled. For example, voltage sources may be enabled in an order from voltage sources having relatively higher nominal voltages to voltage sources having relatively lower voltages, or disabled in an order from voltage sources having relatively lower nominal voltages to voltage sources having relatively higher voltages.Type: ApplicationFiled: February 18, 2022Publication date: August 4, 2022Inventors: Ki-Jun Nam, Takamasa Suzuki, Yantao Ma, Yasushi Matsubara
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Patent number: 11335393Abstract: Disclosed herein is an apparatus that includes a memory cell array including a plurality of memory cells, a first counter circuit configured to periodically update a count value during a first operation mode, a burst clock generator configured to successively generate a burst pulse predetermined times when the count value indicates a predetermined value, and a row address control circuit configured to perform a refresh operation on the memory cell array in response to the burst pulse.Type: GrantFiled: February 10, 2021Date of Patent: May 17, 2022Assignee: Micron Technology, Inc.Inventors: Yoshiro Riho, Yoshinori Matsui, Kiyohiro Furutani, Takahiko Fukiage, Ki-Jun Nam, John D. Porter
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Publication number: 20220129028Abstract: An electronic device may include a main circuit including multiple sub-circuits powered by a direct-current (DC) power supply circuit. The main circuit has a main circuit current demand being a time-varying demand for a DC voltage-regulated supply current being a function of a number of the sub-circuits being active. The DC power supply circuit may include multiple DC voltage regulators to provide the main circuit with the supply current and a command decoding and power management circuit to control enablement of the voltage regulators. The command decoding and power management circuit may be configured to detect an instant value of the main circuit current demand and to selectively enable one or more of the voltage regulators based on the detected instant value.Type: ApplicationFiled: January 7, 2022Publication date: April 28, 2022Inventors: Si Hong Kim, Ki-Jun Nam
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Patent number: 11276455Abstract: A memory device is provided. The memory device includes a memory bank configured to store data in one or more memory cells. The memory device further includes a sense amplifier and associated circuitry configured to detect a first threshold representative of a first external voltage ramping down during a power off of the memory device, and one or more switches triggered via the sense amplifier and associated circuitry to provide for a power off sequence for the memory bank based on using a second external voltage ramping down during the power off of the memory device.Type: GrantFiled: October 28, 2020Date of Patent: March 15, 2022Assignee: Micron Technology, Inc.Inventors: Takamasa Suzuki, Yasushi Matsubara, John D. Porter, Ki-Jun Nam
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Publication number: 20220076725Abstract: Apparatuses and methods related to power domain boundary protection in memory. A number of embodiments can include using a voltage detector to monitor a floating power supply voltage used to power a number of logic components while a memory device operates in a reduced power mode, and responsive to the voltage detector detecting that the floating power supply voltage reaches a threshold value while the memory device is in the reduced power mode, providing a control signal to protection logic to prevent a floating output signal driven from one or more of the logic components from being provided across a power domain boundary to one or more of a different number of logic components.Type: ApplicationFiled: November 11, 2021Publication date: March 10, 2022Inventors: Ki-Jun Nam, Hiroshi Akamatsu, Takamasa Suzuki, Yasushi Matsubara
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Patent number: 11257549Abstract: Methods, systems, and devices for sequential voltage control for a memory device are described. A memory device may have various voltage sources that support different voltage levels used in various operations of the memory device. Voltage sources of a memory device may be disabled under some circumstances, such as when the memory device is idled, or operated in a low-power or powered-down mode, among other circumstances. In accordance with examples as disclosed herein, voltage sources of a memory device or memory die may be sequentially enabled or sequentially disabled. For example, voltage sources may be enabled in an order from voltage sources having relatively higher nominal voltages to voltage sources having relatively lower voltages, or disabled in an order from voltage sources having relatively lower nominal voltages to voltage sources having relatively higher voltages.Type: GrantFiled: May 8, 2020Date of Patent: February 22, 2022Assignee: Micron Technology, Inc.Inventors: Ki-Jun Nam, Takamasa Suzuki, Yantao Ma, Yasushi Matsubara
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Patent number: 11226646Abstract: An electronic device may include a main circuit including multiple sub-circuits powered by a direct-current (DC) power supply circuit. The main circuit has a main circuit current demand being a time-varying demand for a DC voltage-regulated supply current being a function of a number of the sub-circuits being active. The DC power supply circuit may include multiple DC voltage regulators to provide the main circuit with the supply current and a command decoding and power management circuit to control enablement of the voltage regulators. The command decoding and power management circuit may be configured to detect an instant value of the main circuit current demand and to selectively enable one or more of the voltage regulators based on the detected instant value.Type: GrantFiled: June 3, 2020Date of Patent: January 18, 2022Assignee: Micron Technology, Inc.Inventors: Si Hong Kim, Ki-Jun Nam
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Publication number: 20210382511Abstract: An electronic device may include a main circuit including multiple sub-circuits powered by a direct-current (DC) power supply circuit. The main circuit has a main circuit current demand being a time-varying demand for a DC voltage-regulated supply current being a function of a number of the sub-circuits being active. The DC power supply circuit may include multiple DC voltage regulators to provide the main circuit with the supply current and a command decoding and power management circuit to control enablement of the voltage regulators. The command decoding and power management circuit may be configured to detect an instant value of the main circuit current demand and to selectively enable one or more of the voltage regulators based on the detected instant value.Type: ApplicationFiled: June 3, 2020Publication date: December 9, 2021Inventors: Si Hong Kim, Ki-Jun Nam
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Publication number: 20210373648Abstract: Methods, systems, and devices for grouping power supplies for a power saving mode are described to configure a memory device with groups of internal power supplies whose voltage levels may be successively modified according to a group order signaled by an on-die timer. For example, when the memory device enters a deep sleep mode, respective voltage levels of a first group of internal power supplies may be modified to respective external power supply voltage levels at a first time, respective voltage levels of a second group of internal power supplies may be modified to respective external power supply voltage levels at a second time, and so on. When the memory device exits the deep sleep mode, the groups of internal voltage supplies may be modified from the respective external power supply voltage levels to respective operational voltage levels in a group order that is opposite to the entry group order.Type: ApplicationFiled: June 2, 2020Publication date: December 2, 2021Inventors: Ki-Jun Nam, Yantao Ma, Yasushi Matsubara, Takamasa Suzuki
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Patent number: 11176985Abstract: Apparatuses and methods related to power domain boundary protection in memory. A number of embodiments can include using a voltage detector to monitor a floating power supply voltage used to power a number of logic components while a memory device operates in a reduced power mode, and responsive to the voltage detector detecting that the floating power supply voltage reaches a threshold value while the memory device is in the reduced power mode, providing a control signal to protection logic to prevent a floating output signal driven from one or more of the logic components from being provided across a power domain boundary to one or more of a different number of logic components.Type: GrantFiled: July 9, 2020Date of Patent: November 16, 2021Assignee: Micron Technology, Inc.Inventors: Ki-Jun Nam, Hiroshi Akamatsu, Takamasa Suzuki, Yasushi Matsubara