Patents by Inventor Ki Myung Kyung

Ki Myung Kyung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor memory device having a redundancy memory cell array
    Patent number: 8054704
    Abstract: A semiconductor memory device includes a plurality of memory cell mats each comprising a plurality of normal memory cell arrays; and a redundancy memory cell array configured to replace a defective memory cell with a plurality of redundancy memory cells corresponding to a redundancy word line when the redundancy word line corresponding to one or more redundancy memory cell arrays is activated in response to an address corresponding to the defective memory cell among the plurality of normal memory cell arrays.
    Type: Grant
    Filed: June 24, 2009
    Date of Patent: November 8, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Ki-Myung Kyung
  • SEMICONDUCTOR MEMORY DEVICE HAVING SENSE AMPLIFIER
    Publication number: 20110128795
    Abstract: A sense amplifier prevents a reduction in sensing margin occurring when data forms an island pattern. The sense amplifier includes a first inverter having an input terminal connected to a bit line and an output terminal connected to a bar bit line, and a second inverter having an input terminal connected to the bar bit line and an output terminal connected to the bit line. The first and second inverters are configured to receive a pull-up voltage through different pull-up voltage lines, respectively.
    Type: Application
    Filed: December 30, 2009
    Publication date: June 2, 2011
    Inventors: Myoung-Jin LEE, Hyung-Sik Won, Ki-Myung Kyung, Joong-Ho Lee
  • SEMICONDUCTOR MEMORY APPARATUS AND DRIVING METHOD USINGTHE SAME
    Publication number: 20110075495
    Abstract: Various embodiments of a semiconductor memory apparatus and a related driving method are disclosed. According to one exemplary embodiment, a semiconductor memory apparatus may include a switching unit and a switching control unit. The switching unit couples or decouples a cell plate voltage line to or from a cell plate electrode in response to a control signal. The switching control unit is configured to enable the control signal at a first timing and disable the control signal at a second timing.
    Type: Application
    Filed: December 30, 2009
    Publication date: March 31, 2011
    Applicant: Hynix Semiconductor Inc.
    Inventors: Myoung Jin Lee, Ki Myung Kyung
  • Semiconductor Memory Device
    Publication number: 20100290297
    Abstract: A semiconductor memory device includes a plurality of memory cell mats each comprising a plurality of normal memory cell arrays; and a redundancy memory cell array configured to replace a defective memory cell with a plurality of redundancy memory cells corresponding to a redundancy word line when the redundancy word line corresponding to one or more redundancy memory cell arrays is activated in response to an address corresponding to the defective memory cell among the plurality of normal memory cell arrays.
    Type: Application
    Filed: June 24, 2009
    Publication date: November 18, 2010
    Inventor: Ki-Myung Kyung
  • Data I/O line control circuit and semiconductor integrated circuit having the same
    Patent number: 7668026
    Abstract: A data I/O line control circuit includes a control unit for outputting a control signal after a predetermined time from an activation of a column select signal, and a switching unit for selectively separating a pair of first sub-middle I/O lines, which is coupled to a pair of local I/O lines located at one side of the switching unit, from a pair of second sub-middle I/O lines, which is coupled to both the pair of the local I/O lines and a data bus sense amplifier located at the other side of the switching unit.
    Type: Grant
    Filed: December 20, 2007
    Date of Patent: February 23, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Ki Myung Kyung, Jeong Tae Hwang
  • DATA I/O LINE CONTROL CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT HAVING THE SAME
    Publication number: 20080304340
    Abstract: A data I/O line control circuit includes a control unit for outputting a control signal after a predetermined time from an activation of a column select signal, and a switching unit for selectively separating a pair of first sub-middle I/O lines, which is coupled to a pair of local I/O lines located at one side of the switching unit, from a pair of second sub-middle I/O lines, which is coupled to both the pair of the local I/O lines and a data bus sense amplifier located at the other side of the switching unit.
    Type: Application
    Filed: December 20, 2007
    Publication date: December 11, 2008
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Ki Myung Kyung, Jeong Tae Hwang