Patents by Inventor Ki Myung Nam

Ki Myung Nam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10062812
    Abstract: The present invention relates to a method for manufacturing an optical device, and to an optical device manufactured thereby, which involve using a substrate itself as a heat-dissipating plate, and adopting a substrate with vertical insulation layers formed thereon, such that electrode terminals do not have to be extruded out from a sealed space, and thus enabling the overall structure and manufacturing process for an optical device to be simplified.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: August 28, 2018
    Assignee: Point Engineering Co., Ltd.
    Inventors: Ki Myung Nam, Seung Ho Park, Tae Hwan Song
  • Patent number: 10008638
    Abstract: The present invention relates to a method of manufacturing an optical device for a back light unit, and an optical device and an optical device array manufactured by the method, in which optical device chips constituting the optical device array are each laid the sides thereof on a printed circuit board in such a manner that light can be emitted from the optical device chips in a lateral direction, thus reducing the overall thickness of the back light unit.
    Type: Grant
    Filed: May 9, 2013
    Date of Patent: June 26, 2018
    Assignee: Point Engineering Co., Ltd.
    Inventors: Bum Mo Ahn, Seung Ho Park, Ki Myung Nam
  • Patent number: 9847462
    Abstract: Provided is an array substrate for mounting a chip. The array substrate includes a plurality of conductive layers unidirectionally stacked with respect to an original chip substrate; a plurality of insulating layers alternately stacked with the plurality of conductive layers, and electrically separate the plurality of conductive layers; and a cavity having a groove of a predetermined depth with respect to a region including the plurality of insulating layers in an upper surface of the original chip substrate. Accordingly, since the optical device array of a single structure is used as a line source of light, an emission angle emitted from the optical device is great, it is not necessary to form an interval for supplying an amount of light, and a display device can be simply constructed. Further, since it is not necessary to perform soldering a plurality of LED packages on a printed circuit board, a thickness of a back light unit can be reduced.
    Type: Grant
    Filed: October 28, 2014
    Date of Patent: December 19, 2017
    Assignee: Point Engineering Co., Ltd.
    Inventors: Ki Myung Nam, Seung Ho Park, Young Chul Jun
  • Patent number: 9818913
    Abstract: A chip substrate includes at least one insulation portion interposed between conductive portions. A cavity formed in a recessed shape from a region of an upper surface of the chip substrate exposes a top surface of a part of the at least one insulation portion. An insulation layer is coated on the upper surface of the chip substrate excluding the region of the cavity. A bump may be formed at a predetermined height within the cavity.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: November 14, 2017
    Assignee: Point Engineering Co., Ltd.
    Inventors: Ki Myung Nam, Young Woon Jeon, Kyoung Ja Yun
  • Patent number: 9666565
    Abstract: The present invention relates to an optical device and a method for manufacturing the same. The technical object of the invention is to realize a surface emitting body which allows heat generated from a light-emitting chip to be easily dissipated, eliminates the need for an additional wiring layer, and allows a singular light emitting chips or a plurality of light emitting chips to be arranged in series, in parallel, or in series-parallel. The present invention discloses an optical device comprising: a substrate; a plurality of light emitting chips disposed on the substrate; a plurality of conductive wires which electrically connect the substrate with the light emitting chips such that the plurality of light emitting chips are connected to each other in series, in parallel or in series-parallel; and a protective layer which covers the plurality of light emitting chips and the plurality of conductive wires on the substrate.
    Type: Grant
    Filed: January 22, 2016
    Date of Patent: May 30, 2017
    Assignee: Point Engineering Co., Ltd.
    Inventors: Ki Myung Nam, Tae-Hwan Song, Young-Chul Jun
  • Patent number: 9666558
    Abstract: Disclosed is a chip-mounting substrate. The chip-mounting substrate includes a plurality of conductive portions configured to apply voltages to at least two or more chips to be mounted, a plurality of insulation portions formed between the conductive portions and configured to electrically isolate the conductive portions, and a cavity formed in a region which includes at least three or more of the conductive portions and at least two or more of the insulation portions and depressed inward to form a space in which the chips are mounted.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: May 30, 2017
    Assignee: Point Engineering Co., Ltd.
    Inventors: Bum Mo Ahn, Ki Myung Nam, Seung Ho Park
  • Publication number: 20170141274
    Abstract: A chip substrate includes at least one insulation portion interposed between conductive portions. A cavity formed in a recessed shape from a region of an upper surface of the chip substrate exposes a top surface of a part of the at least one insulation portion. An insulation layer is coated on the upper surface of the chip substrate excluding the region of the cavity. A bump may be formed at a predetermined height within the cavity.
    Type: Application
    Filed: January 31, 2017
    Publication date: May 18, 2017
    Inventors: Ki Myung Nam, Young Woon Jeon, Kyoung Ja Yun
  • Patent number: 9653664
    Abstract: Disclosed is a chip substrate. The chip substrate includes: conductive portions laminated in one direction to constitute the chip substrate; insulation portions alternately laminated with the conductive portions to electrically isolate the conductive portions; a cavity formed at a predetermined depth in a recessed shape in a region including the insulation portions on an upper surface of the chip substrate; and a groove portion disposed outside the cavity in a spaced-apart relationship with the cavity and formed at a predetermined depth in a recessed shape. According to the present invention, an adhesive agent is applied in a groove portion formed in advance. It is therefore possible to prevent the adhesive agent from being exposed to the light emitted from optical elements and to prevent the adhesive agent from being denatured. This makes it possible to enhance the reliability of lens bonding. Furthermore, there is no need to use an expensive resistant adhesive agent.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: May 16, 2017
    Assignee: Point Engineering Co., Ltd.
    Inventors: Sin Seok Han, Soo Young Choi, Ki Myung Nam
  • Patent number: 9595642
    Abstract: A chip substrate includes laminated conductive portions, and laminated insulation portions that electrically isolate the conductive portions, with a cavity in a recessed shape in a region including the insulation portions on an upper surface of the chip substrate. The substrate includes an insulation layer on the upper surface, excluding a region of the cavity, and a continuous plating layer along a periphery of the chip substrate on the insulation layer. A portion of a top surface of each insulation portion is exposed in the cavity, and another portion of the top surface of each insulation portion is coated with the insulation layer. A chip package includes a chip substrate, with an optical element sealed in the cavity by a sealing member or lens.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: March 14, 2017
    Assignee: Point Engineering Co., Ltd.
    Inventors: Ki Myung Nam, Young Woon Jeon, Kyoung Ja Yun
  • Patent number: 9559268
    Abstract: A method of manufacturing an optical device for a back light unit includes forming a metal ingot by adhering insulating layers between metal plates. The metal ingot is cut in a vertical direction to create original substrates each with insulating layer portions in parallel with intervals therebetween. Solder resist is deposited on at least one of a top surface and bottom surface of an original substrate.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: January 31, 2017
    Assignee: Point Engineering Co., Ltd.
    Inventors: Bum Mo Ahn, Seung Ho Park, Ki Myung Nam
  • Patent number: 9537074
    Abstract: An optical device substrate includes metal plates and insulating layers formed between the metal plates. Each insulating layer includes a cured insulating layer formed by curing insulating material and an anodized layer merged with each metal plate, the anodized layer formed by anodizing a first metal and a second metal of each metal plate. The first metal and the second metal include a first anodized layer and a second anodized layer, respectively, and are electrically insulated by interfaces including a first interface formed between the first metal and the first anodized layer, a second interface formed between the first anodized layer and the cured insulating layer, a third interface formed between the cured insulating layer and the second metal and a fourth interface formed between the second anodized layer and the second metal.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: January 3, 2017
    Assignee: Point Engineering Co., Ltd.
    Inventors: Ki Myung Nam, Tae Hwan Song, Young Chul Jun
  • Publication number: 20160380168
    Abstract: Disclosed is a chip substrate. The chip substrate includes: conductive portions laminated in one direction to constitute the chip substrate; insulation portions alternately laminated with the conductive portions to electrically isolate the conductive portions; a cavity formed at a predetermined depth in a recessed shape in a region including the insulation portions on an upper surface of the chip substrate; and a groove portion disposed outside the cavity in a spaced-apart relationship with the cavity and formed at a predetermined depth in a recessed shape. According to the present invention, an adhesive agent is applied in a groove portion formed in advance. It is therefore possible to prevent the adhesive agent from being exposed to the light emitted from optical elements and to prevent the adhesive agent from being denatured. This makes it possible to enhance the reliability of lens bonding. Furthermore, there is no need to use an expensive resistant adhesive agent.
    Type: Application
    Filed: June 29, 2015
    Publication date: December 29, 2016
    Inventors: Sin Seok HAN, Soo Young CHOI, Ki Myung NAM
  • Publication number: 20160379957
    Abstract: Disclosed is a chip-mounting substrate. The chip-mounting substrate includes a plurality of conductive portions configured to apply voltages to at least two or more chips to be mounted, a plurality of insulation portions formed between the conductive portions and configured to electrically isolate the conductive portions, and a cavity formed in a region which includes at least three or more of the conductive portions and at least two or more of the insulation portions and depressed inward to form a space in which the chips are mounted.
    Type: Application
    Filed: June 29, 2015
    Publication date: December 29, 2016
    Inventors: Bum Mo AHN, Ki Myung NAM, Seung Ho PARK
  • Publication number: 20160380159
    Abstract: A chip substrate includes laminated conductive portions, and laminated insulation portions that electrically isolate the conductive portions, with a cavity in a recessed shape in a region including the insulation portions on an upper surface of the chip substrate. The substrate includes an insulation layer on the upper surface, excluding a region of the cavity, and a continuous plating layer along a periphery of the chip substrate on the insulation layer. A portion of a top surface of each insulation portion is exposed in the cavity, and another portion of the top surface of each insulation portion is coated with the insulation layer. A chip package includes a chip substrate, with an optical element sealed in the cavity by a sealing member or lens.
    Type: Application
    Filed: June 29, 2015
    Publication date: December 29, 2016
    Inventors: Ki Myung NAM, Young Woon JEON, Kyoung Ja YUN
  • Publication number: 20160204323
    Abstract: The present invention relates to an optical device and a method for manufacturing the same. The technical object of the invention is to realize a surface emitting body which allows heat generated from a light-emitting chip to be easily dissipated, eliminates the need for an additional wiring layer, and allows a singular light emitting chips or a plurality of light emitting chips to be arranged in series, in parallel, or in series-parallel. The present invention discloses an optical device comprising: a substrate; a plurality of light emitting chips disposed on the substrate; a plurality of conductive wires which electrically connect the substrate with the light emitting chips such that the plurality of light emitting chips are connected to each other in series, in parallel or in series-parallel; and a protective layer which covers the plurality of light emitting chips and the plurality of conductive wires on the substrate.
    Type: Application
    Filed: January 22, 2016
    Publication date: July 14, 2016
    Inventors: Ki Myung Nam, Tae-Hwan Song, Young-Chul Jun
  • Publication number: 20160190398
    Abstract: The present invention relates to a method for manufacturing an optical device, and to an optical device manufactured thereby, which involve using a substrate itself as a heat-dissipating plate, and adopting a substrate with vertical insulation layers formed thereon, such that electrode terminals do not have to be extruded out from a sealed space, and thus enabling the overall structure and manufacturing process for an optical device to be simplified.
    Type: Application
    Filed: December 31, 2015
    Publication date: June 30, 2016
    Inventors: Ki Myung Nam, Seung Ho Park, Tae Hwan Song
  • Patent number: 9378986
    Abstract: Provided is a method of mounting a chip. The method includes: forming a bump at one surface of a cavity formed concavely in an inner direction of a substrate; performing a coining process to flatten a surface of the bump; coating a solder material on the bump subjected to the coining process; and bonding a chip and the bump by melting the solder material, wherein an electrode portion or a metal portion is formed on a bottom of the chip. For a metal substrate according to the present invention, wherein a vertical insulating layer is included, since the electrode portion of the chip and the electrode portion of the substrate have to be electrically connected, the metal substrate is bonded to the electrode portion of the chip using the bump additionally formed on the metal substrate, so the heat generated in the chip can be rapidly transferred to the substrate, and the junction temperature of the chip can be decreased, thereby enhancing the light efficiency and the.
    Type: Grant
    Filed: October 10, 2014
    Date of Patent: June 28, 2016
    Assignee: Point Engineering Co., Inc.
    Inventors: Bum Mo Ahn, Ki Myung Nam, Seung Ho Park
  • Patent number: 9374890
    Abstract: A chip substrate includes: a conductive layer being stacked in one direction and constituting a chip substrate; an insulator being alternately stacked with the conductive layer and electrically separating the conductive layer; and a lens insert having: a depression reaching down to a predetermined depth from a specified area of an upper surface of the chip substrate overlapping with the insulator; and a predetermined number of sides on the upper surface wherein arcs are formed at regions where the sides are met with each other. Since the space for inserting a lens can be formed to have a shape comprising straight lines, and a lens to be inserted can also be manufactured in a shape comprising straight lines, therefore the manufacturing process for a lens to be inserted into the chip substrate can be further simplified.
    Type: Grant
    Filed: November 18, 2014
    Date of Patent: June 21, 2016
    Assignee: Point Engineering Co., Ltd.
    Inventors: Bum Mo Ahn, Ki Myung Nam, Young Chul Jun
  • Patent number: 9316768
    Abstract: A substrate for an optical device includes an optical device substrate including a plurality of conductive plates elongated along a length direction, wherein side surfaces of the conductive plates are bonded to each other with insulators interposed therebetween, the insulators being respectively formed on the side surfaces. A groove having a predetermined depth for preventing burrs is formed in a lower surface of the optical device substrate at each point where a cutting line is crossed with one of the insulators when the optical device substrate is cut in a length direction and in a vertical direction, the groove being formed in such a way that said one of the insulators is exposed to an inside of the groove.
    Type: Grant
    Filed: November 18, 2014
    Date of Patent: April 19, 2016
    Assignee: Point Engineering Co., Ltd.
    Inventors: Bum Mo Ahn, Ki Myung Nam, Kyung Soo Yoo
  • Patent number: 9306142
    Abstract: The manufacturing of an optical device substrate is achieved by anodizing the surface of a metal plate, coating an insulative liquid bonding agent, having a viscosity which can permeate into an anodized film of the metal plate, on the metal plate, and alternately layering, pressing, and heat treating the metal plate coated with the liquid bonding agent and an insulative film bonding agent before the liquid bonding agent becomes solid so that bonding force between the metal plate and an insulation layer is strengthened, bubbles formation in the liquid bonding agent is inhibited, the fragile nature of the liquid bonding agent after the solidification is reduced producing an optical device substrate with improved mechanical strength and an insulation layer of precisely controlled thickness.
    Type: Grant
    Filed: November 23, 2011
    Date of Patent: April 5, 2016
    Assignee: Point Engineering Co., Ltd.
    Inventors: Ki Myung Nam, Tae Hwan Song, Young Chul Jun