Abstract: A reconfigurable processor includes a plurality of mini-cores and an external network to which the mini-cores are connected. Each of the mini-cores includes a first function unit including a first group of operation elements, a second function unit including a second group of operation elements that is different from the first group of operation elements, and an internal network to which the first function unit and the second function unit are connected.

Abstract: A technology for controlling a reconfigurable processor is provided. The reconfigurable processor dynamically loads configuration data from a peripheral memory to a configuration memory while a program is being executed, in place of loading all compiled configuration data in advance into the configuration memory when booting commences. Accordingly, a reduction in capacity of a configuration memory may be achieved.

Abstract: Provided is a memory controller that manages memory access requests between the processor and the memory. In response to the memory controller receiving two or more memory access requests for the same area of memory, the memory controller is configured to stall the memory controller and sequentially process the memory access requests.

Abstract: A direct memory access (DMA) controller is provided. The DMA controller includes a processor interface configured to directly receive information representing a first operation sent by a processor to a buffer, and transmit data corresponding to the first operation stored in the buffer to the processor core or record data corresponding to the first operation in the buffer, and a buffer group connected to the processor interface, and including a plurality of buffers.

Abstract: A method of controlling a processor includes receiving from a command buffer a first command corresponding to a first instruction that is processed by a second processing core and starting processing of the first command by the first processing core, storing in the command buffer a second command corresponding to a second instruction that is processed by the second processing core before the processing of the first command is completed, and starting processing of a third instruction by the second processing core before the processing of the first command is completed.

Abstract: Provided is a processor with a heterogeneous clustered architecture. The processor comprises a first cluster comprising a first functional unit configured to process a first type of instruction, and a register whose I/O ports are connected to I/O ports of the functional unit; and a second cluster comprising a second functional unit configured to process the first type of instruction and second type of instruction, and a second register whose I/O ports are connected to I/O ports of the second functional unit.

Abstract: A reconfigurable processor and an operation method thereof are provided. The reconfigurable processor may include: a controller configured to control operations of a first mode, in which a first portion of a program that does not utilize loop acceleration is processed, and a second mode, in which a second portion for the program that utilizes the loop acceleration is processed, based on whether an instruction to control parallel operations of the first mode and the second mode is executed; and a shared register file configured to transfer data between the first mode and the second mode.

Abstract: An apparatus and method capable of reducing idle resources in a multicore device and improving the use of available resources in the multicore device are provided. The apparatus includes a static scheduling unit configured to generate one or more task groups, and to allocate the task groups to virtual cores by dividing or combining the tasks included in the task groups based on the execution time estimates of the task groups. The apparatus also includes a dynamic scheduling unit configured to map the virtual cores to physical cores.

Abstract: A multiport data cache apparatus and a method of controlling the same are provided. The multiport data cache apparatus includes a plurality of cache banks configured to share a cache line, and a data cache controller configured to receive cache requests for the cache banks, each of which including a cache bank identifier, transfer the received cache requests to the respective cache banks according to the cache bank identifiers, and process the cache requests independently from one another.

Abstract: A reconfigurable processor includes a plurality of mini-cores and an external network to which the mini-cores are connected. Each of the mini-cores includes a first function unit including a first group of operation elements, a second function unit including a second group of operation elements that is different from the first group of operation elements, and an internal network to which the first function unit and the second function unit are connected.

Abstract: Provided is a memory controller that manages memory access requests between the processor and the memory. In response to the memory controller receiving two or more memory access requests for the same area of memory, the memory controller is configured to stall the memory controller and sequentially process the memory access requests.

Abstract: A processor, apparatus and method to use a multiple store instruction based on physical addresses of registers are provided. The processor is configured to execute an instruction to store data of a plurality of registers in a memory, the instruction including a first area in which a physical address of each of the registers is written. An instruction generating apparatus is configured to generate an instruction to store data of a plurality of registers in a memory, the instruction including a first area in which a physical address of each of the registers is written. An instruction generating method includes detecting a code area that instructs to store data of a plurality of registers in a memory, from a program code. The instruction generating method further includes generating an instruction corresponding to the code area by mapping physical addresses of the registers to a first area of the instruction.

Abstract: Provided is a Direct Memory Access (DMA) controller which provides a function of searching for a specific pattern from data being transmitted during DMA transmission. The DMA controller stores at least one pattern value. The DMA controller compares data being transmitted to a pattern value while transmitting the data using a DMA method, and generates, in response to data matching the pattern value being detected, a signal indicating that the data matching the pattern value has been detected. The DMA controller stores an address of the data matching the pattern value in response to the generated signal.

Abstract: An apparatus and method capable of reducing idle resources in a multicore device and improving the use of available resources in the multicore device are provided. The apparatus includes a static scheduling unit configured to generate one or more task groups, and to allocate the task groups to virtual cores by dividing or combining the tasks included in the task groups based on the execution time estimates of the task groups. The apparatus also includes a dynamic scheduling unit configured to map the virtual cores to physical cores.

Abstract: A multiport data cache apparatus and a method of controlling the same are provided. The multiport data cache apparatus includes a plurality of cache banks configured to share a cache line, and a data cache controller configured to receive cache requests for the cache banks, each of which including a cache bank identifier, transfer the received cache requests to the respective cache banks according to the cache bank identifiers, and process the cache requests independently from one another.

Abstract: Provided is a Direct Memory Access (DMA) controller which provides a function of searching for a specific pattern from data being transmitted during DMA transmission. The DMA controller stores at least one pattern value. The DMA controller compares data being transmitted to a pattern value while transmitting the data using a DMA method, and generates, in response to data matching the pattern value being detected, a signal indicating that the data matching the pattern value has been detected. The DMA controller stores an address of the data matching the pattern value in response to the generated signal.

Abstract: A technology for controlling a reconfigurable processor is provided. The reconfigurable processor dynamically loads configuration data from a peripheral memory to a configuration memory while a program is being executed, in place of loading all compiled configuration data in advance into the configuration memory when booting commences. Accordingly, a reduction in capacity of a configuration memory may be achieved.