Abstract: A method for evaluating the dispersibility of a conductive material. The method allows determination of the dispersibility of a conductive material in an electrode as a quantitative value. Particularly, a conductive material zone is defined from the result (2D mapping image) obtained by subjecting an optional predetermined cross-section of electrode active material layer to 2D-scale visual image processing, and then the circumference and area of the portion defined as the conductive material zone are calculated. In this manner, the dispersibility of the conductive material can be represented quantitatively.

Abstract: A semiconductor memory device with improved performance by improving interface characteristics while reducing a leakage current, and a method for fabricating the same are provided. The semiconductor memory device includes a conductive line on a substrate, a first interlayer insulating layer exposing the conductive line and defining a channel trench on the substrate, a channel layer extending along a bottom and side surface of the channel trench, a first gate electrode and a second gate electrode spaced apart from each other in the channel trench, a first gate insulating layer between the channel layer and the first gate electrode, and a second gate insulating layer between the channel layer and the second gate electrode. The channel layer includes a first oxide semiconductor layer and a second oxide semiconductor layer sequentially stacked on the conductive line. The first oxide semiconductor layer has a greater crystallinity than the second oxide semiconductor layer.

Abstract: Semiconductor memory devices including capacitors and methods for manufacturing thereof. The semiconductor memory device may include a substrate, an element isolation pattern defining an active area in the substrate, a first conductive pattern on the substrate and the element isolation pattern, and extending in a first direction, wherein the first conductive pattern is connected to a first portion of the active area, a capacitor structure on the substrate and the element isolation pattern and connected to a second portion of the active area, a gate trench defined in the substrate and the element isolation pattern and extending in a second direction, wherein a first trench width of a portion of the gate trench in the active area is greater than a second trench width of a portion of the gate trench in the element isolation pattern.

Abstract: Provided is a semiconductor memory device. The semiconductor memory device includes a substrate, a channel region on the substrate, first and second source/drain regions electrically connected to the channel region, a gate electrode that extends in a first direction and is on the channel region, a conductive line that extends in a second direction intersecting the first direction and is electrically connected to the second source/drain region, and a capacitor structure electrically connected to the first source/drain region on the substrate. The capacitor structure may include a plurality of first electrodes stacked and spaced apart from each other in a third direction perpendicular to an upper surface of the substrate, a plurality of trenches extending into the plurality of first electrodes, a capacitor dielectric film that extends along side walls of each of the plurality of trenches, and a plurality of second electrodes in the plurality of trenches, respectively.

Abstract: A semiconductor memory device includes a substrate comprising an element isolation layer, a bit line that extends on the substrate in a first direction, a cell buffer insulating layer between the bit line and the substrate and comprising an upper cell buffer insulating layer and a lower cell buffer insulating layer, a lower storage contact disposed on a plurality of sides of the bit line and comprising a semiconductor epitaxial pattern, a storage pad on the lower storage contact and connected to the lower storage contact and an information storage unit on the storage pad and connected to the storage pad, wherein the upper cell buffer insulating layer is between the lower cell buffer insulating layer and the bit line, and each of the lower cell buffer insulating layer and the upper cell buffer insulating layer comprises an upper surface and a lower surface that are opposite to each other.

Abstract: There is provided a semiconductor memory device comprising: a substrate; a base insulating film on an upper surface of the substrate; a plurality of first conductive patterns on the base insulating film and spaced apart from each other, wherein the plurality of first conductive patterns extend in a first direction; a spacer structure on a side surface of each of the plurality of first conductive patterns; a barrier metal film on a side surface of the spacer structure, wherein the barrier metal film extends through the base insulating film to be electrically connected to the substrate; a filling metal film on the barrier metal film, wherein the filling metal film fills at least a portion of a space between adjacent ones of the plurality of first conductive patterns; and a capacitor structure on the filling metal film, wherein the capacitor structure is electrically connected to the filling metal film.

Abstract: An epitaxial wafer is disclosed. The epitaxial wafer includes a substrate; and a stack structure disposed on the substrate, wherein the stack structure includes first and second layers alternately stacked on top of each other, wherein the first layer is made of a compound represented by one selected from a group consisting of following Chemical Formulas 1-1 to 1-5, wherein the second layer is made of a compound represented by a following Chemical Formula 2: Si1-xGex(m?x?1.0)??[Chemical Formula 1-1] Si1-x-yGexBy(m?x<1.0,0<y?0.4,0.2<x+y?1.0)??[Chemical Formula 1-2] Si1-x-zGexPz(m?x<1.0,0<z?0.4,0.2<x+z?1.0)??[Chemical Formula 1-3] Si1-x-zGexCz(m?x<1.0,0<z?0.4,0.2<x+z?1.0)??[Chemical Formula 1-4] Si1-x-y-zGexByPz(0.2<x<1.0,0<y?0.4,0<z?0.4,0.2<x+y+z?1.

Abstract: A semiconductor memory device with improved integration and electrical characteristics. The semiconductor memory device includes a peri-gate structure, a first peri-connecting structure on the peri-gate structure, a data storage pattern on the first peri-connecting structure, an active pattern that includes a first surface and a second surface opposite to each other in a first direction, and a first side wall and a second side wall opposite to each other in a second direction, the first surface of the active pattern connected to the data storage pattern and facing a substrate, a bit line on the active pattern, connected to the second surface of the active pattern, and extends in the second direction, a word line on the first side wall of the active pattern and extending in a third direction, a second peri-connecting structure connected to the bit line and a connecting pad connected to the second peri-connecting wiring.

Abstract: A semiconductor device includes a lower substrate, a memory cell structure including a wordline on the lower substrate, a bitline disposed on the lower substrate and intersecting the wordline, and a cell capacitor connected to the lower substrate, an upper substrate having a back side adjacent to the lower substrate and a front side opposite to the back side, a circuit element disposed on the front side of the upper substrate and overlapping the memory cell structure in a vertical direction, and a through via penetrating the upper substrate and electrically connecting the memory cell structure and the circuit element with each other.

Abstract: A semiconductor memory device includes a peri-gate structure on a substrate, a first bonding pad on the peri-gate structure, a shielding conductive pattern on the first bonding pad, a second bonding pad between the shielding conductive pattern and the first bonding pad and contacting the first bonding pad, a bit line on the shielding conductive pattern extending in a first direction, an active pattern on the bit line and including a lower surface and an upper surface, and a first side wall and a second side wall opposite to each other in the first direction, the lower surface of the active pattern being connected to the bit line, a word line on the first side wall of the active pattern, and extends in a third direction, and a data storage pattern on the active pattern, and is connected to the upper surface of the active pattern.

Abstract: A semiconductor memory device including an active pattern on a first substrate and comprising a first and second surfaces opposite to each other in a first direction, a data storage pattern between the active pattern and the first substrate and connected to a first surface of the active pattern, a bit line on the active pattern, connected to a second surface of the active pattern, and extending in a second direction, a word line on a sidewall of the active pattern, a second substrate, a peripheral gate structure on a first surface of the second substrate, a first connection wiring structure on the first surface of the second substrate and connected to the peripheral gate structure and bit line, a second connection wiring structure on a second surface of the second substrate and a through via penetrating the second substrate and connecting the first and second connection wiring structures.

Abstract: A semiconductor memory device with improved performance by improving interface characteristics while reducing a leakage current, and a method for fabricating the same are provided. The semiconductor memory device includes a conductive line on a substrate, a first interlayer insulating layer exposing the conductive line and defining a channel trench on the substrate, a channel layer extending along a bottom and side surface of the channel trench, a first gate electrode and a second gate electrode spaced apart from each other in the channel trench, a first gate insulating layer between the channel layer and the first gate electrode, and a second gate insulating layer between the channel layer and the second gate electrode. The channel layer includes a first oxide semiconductor layer and a second oxide semiconductor layer sequentially stacked on the conductive line. The first oxide semiconductor layer has a greater crystallinity than the second oxide semiconductor layer.

Abstract: The present disclosure relates to a conductive material master batch for use in an electrode and an electrode obtained by using the same. The electrode obtained by using the conductive material master batch has an electrode resistance of 55 ohm·cm or less.

Abstract: Provided a semiconductor memory device. The semiconductor memory device includes a substrate, a gate electrode on the substrate, a bit line on the substrate, a cell semiconductor pattern on a side of the gate electrode and electrically connected to the bit line, a capacitor structure including a first electrode electrically connected to the cell semiconductor pattern, a second electrode on the first electrode, and a capacitor dielectric film between the first electrode and the second electrode, a bit line strapping line spaced apart from the bit line in the second direction, and electrically connected to the bit line, a bit line selection line between the bit line and the bit line strapping line, and a selection semiconductor pattern between the bit line and the bit line strapping line and electrically connected to all of the bit line, the bit line strapping line, and the bit line selection line.

Abstract: A powder for an electrode for manufacturing a dry electrode for a secondary battery, including an active material, a conductive material and a binder, and showing a resistivity of 700 ?·cm or less when being pressurized under a pressure of 50 MPa. The present disclosure also relates to a method for preparing the powder for an electrode, a method for manufacturing a dry electrode using the powder for an electrode, a dry electrode, a secondary battery including the dry electrode, an energy storage apparatus.

Abstract: A semiconductor memory device includes a peripheral gate structure disposed on a substrate, a bit line disposed on the peripheral gate structure and extending in a first direction, a shielding structure disposed adjacent to the bit line on the peripheral gate structure and extending in the first direction, a first word line disposed on the bit line and the shielding structure and extending in a second direction, a second word line disposed on the bit line and the shielding structure, extending in the second direction, and spaced apart from the first word line in the first direction, first and second active patterns disposed on the bit line and disposed between the first and second word lines, and contact patterns connected to the first and second active patterns.

Abstract: [summary] An epitaxial wafer is disclosed. The epitaxial wafer includes a substrate; and a stack disposed on the substrate, wherein the stack includes silicon (Si) layers and silicon germanium (SiGe) layers alternately stacked on top of each other, wherein the silicon germanium layer is doped with boron (B) or phosphorus (P).

Abstract: A flow controllable type suction and irrigation device includes: a handle having an installation space therein; a cannula provided with a conductive tube and an insulating protective tube, the conductive tube extending in a forward direction of the handle to be inserted into the abdominal cavity of a patient and being coupled to an electrode for surgery, the insulating protective tube being disposed to surround the conductive tube; and a suction supply unit provided to the handle and supplying an irrigation fluid to the cannula or suctioning blood or contaminants from the abdominal cavity of the patient through the cannula.

Abstract: A includes an element isolation region, a first active region bounded by the element isolation region and that extends in a first direction and includes first and second parts disposed at a first level, and a third part disposed at a second level located above the first level, and a gate electrode disposed inside each of the element isolation region and the first active region and that extends in a second direction different from the first direction. The second part is spaced apart in the first direction from the first part, and the third part contacts each of the first and second parts. A first width in the second direction of the first part is less than a second width in the second direction of the third part.

Abstract: According to some embodiments of the present inventive concept, a semiconductor memory device includes a plurality of mold insulating layers on a substrate and spaced apart from one another, a plurality of semiconductor patterns which are between respective ones of the plurality of mold insulating layers adjacent to each other, a plurality of gate electrodes, on respective ones of the plurality of semiconductor patterns, an information storage element which includes a first electrode electrically connected to each of the plurality of semiconductor patterns, a second electrode on the first electrode, and a capacitor dielectric film between the first electrode and the second electrode, a bit line on the substrate and contacts the semiconductor pattern, and an insulating buffer film between the first electrodes and the second electrode and on a sidewall of a respective one of the plurality of mold insulating layers.