Patents by Inventor Kiseok Suh
Kiseok Suh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10418548Abstract: A method of fabricating a magnetic memory device includes forming an interlayered insulating layer on a substrate, forming a landing pad to pass through the interlayered insulating layer, forming a protection insulating layer on the interlayered insulating layer to cover a top surface of the landing pad, forming a bottom electrode to pass through the protection insulating layer and through the interlayered insulating layer, forming a magnetic tunnel junction layer on the protection insulating layer; and patterning the magnetic tunnel junction layer to form a magnetic tunnel junction pattern on the bottom electrode.Type: GrantFiled: June 26, 2018Date of Patent: September 17, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Shinhee Han, Kiseok Suh, KyungTae Nam, Woojin Kim, Kwangil Shin, Minkyoung Joo, Gwanhyeob Koh
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Patent number: 10283698Abstract: A device, which may include a semiconductor device, may include a contact plug, a first barrier metal covering a bottom surface of the contact plug and a lower sidewall of the contact plug, such that the first barrier metal exposes an upper sidewall of the contact plug, and an insulation pattern covering the upper sidewall of the contact plug such that the insulation pattern isolates the first barrier metal from exposure. A magnetic tunnel junction pattern may cover a top surface of the contact plug. Each element of the contact plug, the first barrier metal, and the insulation pattern may be in a contact hole of a first interlayer dielectric layer.Type: GrantFiled: August 2, 2017Date of Patent: May 7, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Seung Pil Ko, Kiseok Suh, Kilho Lee, Daeeun Jeong
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Patent number: 10164170Abstract: A first lower interconnection structure and a second lower interconnection structure are formed using a first design rule on a first region of a substrate and a second region of the substrate, respectively. A memory element is formed on the first lower interconnection structure. The memory element includes a bottom electrode, a magnetic tunnel junction and a top electrode stacked on each other. An upper conductive line and an upper interconnection line are formed using a second design rule larger than the first design rule on the first lower interconnection structure and the second lower interconnection structure, respectively. The first lower interconnection structure, the memory element and the upper conductive line are stacked on each other so that the memory element is interposed between the first lower interconnection structure and the upper conductive line.Type: GrantFiled: June 13, 2017Date of Patent: December 25, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kiseok Suh, Byoungjae Bae, Gwanhyeob Koh, Yoonjong Song, Kilho Lee
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Publication number: 20180309052Abstract: A method of fabricating a magnetic memory device includes forming an interlayered insulating layer on a substrate, forming a landing pad to pass through the interlayered insulating layer, forming a protection insulating layer on the interlayered insulating layer to cover a top surface of the landing pad, forming a bottom electrode to pass through the protection insulating layer and through the interlayered insulating layer, forming a magnetic tunnel junction layer on the protection insulating layer; and patterning the magnetic tunnel junction layer to form a magnetic tunnel junction pattern on the bottom electrode.Type: ApplicationFiled: June 26, 2018Publication date: October 25, 2018Inventors: Shinhee HAN, Kiseok SUH, KyungTae NAM, Woojin KIM, Kwangil SHIN, Minkyoung JOO, Gwanhyeob KOH
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Patent number: 10032981Abstract: A method of fabricating a magnetic memory device includes forming an interlayered insulating layer on a substrate, forming a landing pad to pass through the interlayered insulating layer, forming a protection insulating layer on the interlayered insulating layer to cover a top surface of the landing pad, forming a bottom electrode to pass through the protection insulating layer and through the interlayered insulating layer, forming a magnetic tunnel junction layer on the protection insulating layer; and patterning the magnetic tunnel junction layer to form a magnetic tunnel junction pattern on the bottom electrode.Type: GrantFiled: August 23, 2016Date of Patent: July 24, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Shinhee Han, Kiseok Suh, KyungTae Nam, Woojin Kim, Kwangil Shin, Minkyoung Joo, Gwanhyeob Koh
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Publication number: 20180198059Abstract: A device, which may include a semiconductor device, may include a contact plug, a first barrier metal covering a bottom surface of the contact plug and a lower sidewall of the contact plug, such that the first barrier metal exposes an upper sidewall of the contact plug, and an insulation pattern covering the upper sidewall of the contact plug such that the insulation pattern isolates the first barrier metal from exposure. A magnetic tunnel junction pattern may cover a top surface of the contact plug. Each element of the contact plug, the first barrier metal, and the insulation pattern may be in a contact hole of a first interlayer dielectric layer.Type: ApplicationFiled: August 2, 2017Publication date: July 12, 2018Inventors: Seung Pil KO, Kiseok SUH, Kilho LEE, Daeeun JEONG
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Publication number: 20180159023Abstract: A first lower interconnection structure and a second lower interconnection structure are formed using a first design rule on a first region of a substrate and a second region of the substrate, respectively. A memory element is formed on the first lower interconnection structure. The memory element includes a bottom electrode, a magnetic tunnel junction and a top electrode stacked on each other. An upper conductive line and an upper interconnection line are formed using a second design rule larger than the first design rule on the first lower interconnection structure and the second lower interconnection structure, respectively. The first lower interconnection structure, the memory element and the upper conductive line are stacked on each other so that the memory element is interposed between the first lower interconnection structure and the upper conductive line.Type: ApplicationFiled: June 13, 2017Publication date: June 7, 2018Inventors: Kiseok SUH, BYOUNGJAE BAE, GWANHYEOB KOH, YOONJONG SONG, KILHO LEE
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Patent number: 9911787Abstract: A semiconductor device includes an active region defining an isolation region. First and second cell interconnection structures are on the active region and the isolation region, and have line shapes that are parallel to each other. An isolation pattern is on the active region and the isolation region. The isolation pattern is between the first and second cell interconnection structures. Contact structures are between the first and second cell interconnection structures. The contact structures are at both sides of the isolation pattern and overlap the active region. Insulating patterns are between the first and second cell interconnection structures. The insulating patterns are at both sides of the isolation pattern and overlap the isolation region. Common source regions are under the first and second cell interconnection structures. The common source regions are in the active region. An isolating gate pattern that has a line shape is under the isolation pattern.Type: GrantFiled: June 21, 2016Date of Patent: March 6, 2018Assignee: Samsung Electronics Co, Ltd.Inventors: Kiseok Suh, Gwanhyeob Koh, Yoonjong Song
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Publication number: 20170324025Abstract: A data storage device and a method for manufacturing the data storage device provide a data storage device having a superior reliability and easy fabrication. The data storage device comprises a substrate including cell and peripheral circuit regions, a first conductive line on the peripheral circuit region, a peripheral contact plug between the substrate and the first conductive line, the peripheral contact plug being in contact with the first conductive line, a second conductive line on the cell region, a plurality of data storage structures between the substrate and the second conductive line, and a wiring structure between the substrate and each of the data storage structures and between the substrate and the peripheral contact plug. The first conductive line includes a bottom surface having a position from the substrate that is lower than a position of a bottom surface of the second conductive line.Type: ApplicationFiled: February 17, 2017Publication date: November 9, 2017Inventors: KILHO LEE, Kiseok SUH, Yoonsung HAN, GWANHYEOB KOH, YOONJONG SONG
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Patent number: 9806028Abstract: A semiconductor memory device includes a device isolation in a trench that defines first to third active patterns that are spaced apart from each other and having a long axis parallel to a first direction, first and second word lines extending in a second direction perpendicular to the first direction, a bit line, and a source line. The first and second active patterns are arranged in the second direction to constitute a column. The third active pattern is at a side of the column. The first word line intersects the first and second active patterns. The second word line intersects the third active pattern. When viewed from a plan view, the bit line extends in the first direction between the first and third active patterns, and the source line extends in the first direction between the second and third active patterns.Type: GrantFiled: July 6, 2015Date of Patent: October 31, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Jaekyu Lee, Kiseok Suh
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Patent number: 9711716Abstract: A magnetic memory device and a method for manufacturing the magnetic memory device are disclosed. The method includes forming a first interlayer insulating layer on a substrate, forming a first conductive pattern that penetrates the first interlayer insulating layer, forming a mold insulating layer that includes first and second mold insulating layers on the first interlayer insulating layer, forming a second conductive pattern that penetrates the first and second mold insulating layers and the first interlayer insulating layer, and forming a magnetic tunnel junction pattern on the second conductive pattern. The first mold insulating layer is in contact with the first conductive pattern, and the second mold insulating layer is disposed on the first mold insulating layer.Type: GrantFiled: August 24, 2016Date of Patent: July 18, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Myoungsu Son, Kiseok Suh, Gwanhyeob Koh, KyungTae Nam, Yoonjong Song
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Publication number: 20170110507Abstract: A semiconductor device includes an active region defining an isolation region. First and second cell interconnection structures are on the active region and the isolation region, and have line shapes that are parallel to each other. An isolation pattern is on the active region and the isolation region. The isolation pattern is between the first and second cell interconnection structures. Contact structures are between the first and second cell interconnection structures. The contact structures are at both sides of the isolation pattern and overlap the active region. Insulating patterns are between the first and second cell interconnection structures. The insulating patterns are at both sides of the isolation pattern and overlap the isolation region. Common source regions are under the first and second cell interconnection structures. The common source regions are in the active region. An isolating gate pattern that has a line shape is under the isolation pattern.Type: ApplicationFiled: June 21, 2016Publication date: April 20, 2017Inventors: Kiseok SUH, Gwanhyeob Koh, Yoonjong Song
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Patent number: 9620190Abstract: A magnetic memory device can include a plurality of separately controllable magnetic memory segments configured to store data. A plurality of separately controllable source lines can each be coupled to a respective one of the plurality of separately controllable magnetic memory segments.Type: GrantFiled: January 30, 2015Date of Patent: April 11, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Jaekyu Lee, Kiseok Suh
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Publication number: 20170092851Abstract: A method of fabricating a magnetic memory device includes forming an interlayered insulating layer on a substrate, forming a landing pad to pass through the interlayered insulating layer, forming a protection insulating layer on the interlayered insulating layer to cover a top surface of the landing pad, forming a bottom electrode to pass through the protection insulating layer and through the interlayered insulating layer, forming a magnetic tunnel junction layer on the protection insulating layer; and patterning the magnetic tunnel junction layer to form a magnetic tunnel junction pattern on the bottom electrode.Type: ApplicationFiled: August 23, 2016Publication date: March 30, 2017Inventors: Shinhee HAN, Kiseok SUH, KyungTae NAM, Woojin KIM, Kwangil SHIN, Minkyoung JOO, Gwanhyeob KOH
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Publication number: 20170092852Abstract: A magnetic memory device and a method for manufacturing the magnetic memory device are disclosed. The method includes forming a first interlayer insulating layer on a substrate, forming a first conductive pattern that penetrates the first interlayer insulating layer, forming a mold insulating layer that includes first and second mold insulating layers on the first interlayer insulating layer, forming a second conductive pattern that penetrates the first and second mold insulating layers and the first interlayer insulating layer, and forming a magnetic tunnel junction pattern on the second conductive pattern. The first mold insulating layer is in contact with the first conductive pattern, and the second mold insulating layer is disposed on the first mold insulating layer.Type: ApplicationFiled: August 24, 2016Publication date: March 30, 2017Inventors: Myoungsu SON, Kiseok SUH, GWANHYEOB KOH, KyungTae NAM, YOONJONG SONG
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Publication number: 20160086882Abstract: A semiconductor memory device includes a device isolation in a trench that defines first to third active patterns that are spaced apart from each other and having a long axis parallel to a first direction, first and second word lines extending in a second direction perpendicular to the first direction, a bit line, and a source line. The first and second active patterns are arranged in the second direction to constitute a column. The third active pattern is at a side of the column. The first word line intersects the first and second active patterns. The second word line intersects the third active pattern. When viewed from a plan view, the bit line extends in the first direction between the first and third active patterns, and the source line extends in the first direction between the second and third active patterns.Type: ApplicationFiled: July 6, 2015Publication date: March 24, 2016Inventors: Jaekyu LEE, Kiseok SUH
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Publication number: 20150294695Abstract: A magnetic memory device can include a plurality of separately controllable magnetic memory segments configured to store data. A plurality of separately controllable source lines can each be coupled to a respective one of the plurality of separately controllable magnetic memory segments.Type: ApplicationFiled: January 30, 2015Publication date: October 15, 2015Inventors: Jaekyu Lee, Kiseok Suh
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Patent number: 8901009Abstract: A memory device includes a lower interconnection in a semiconductor substrate, the lower interconnection being made of a material different from the semiconductor substrate, a selection element on the lower interconnection, and a memory element on the selection element.Type: GrantFiled: December 19, 2013Date of Patent: December 2, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Jaekyu Lee, Kiseok Suh, Tae Eung Yoon
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Publication number: 20140106535Abstract: A memory device includes a lower interconnection in a semiconductor substrate, the lower interconnection being made of a material different from the semiconductor substrate, a selection element on the lower interconnection, and a memory element on the selection element.Type: ApplicationFiled: December 19, 2013Publication date: April 17, 2014Applicant: Samsung Electronics Co., Ltd.Inventors: Jaekyu LEE, Kiseok SUH, Tae Eung YOON
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Patent number: 8614433Abstract: A memory device includes a lower interconnection in a semiconductor substrate, the lower interconnection being made of a material different from the semiconductor substrate, a selection element on the lower interconnection, and a memory element on the selection element.Type: GrantFiled: May 3, 2012Date of Patent: December 24, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Jaekyu Lee, Kiseok Suh, Tae Eung Yoon