Patents by Inventor Ki Soo Choi
Ki Soo Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11957669Abstract: One aspect of the present disclosure is a pharmaceutical composition which includes (R)—N-[1-(3,5-difluoro-4-methansulfonylamino-phenyl)-ethyl]-3-(2-propyl-6-trifluoromethyl-pyridin-3-yl)-acrylamide as a first component and a cellulosic polymer as a second component, wherein the composition of one aspect of the present disclosure has a formulation characteristic in which crystal formation is delayed for a long time.Type: GrantFiled: August 10, 2018Date of Patent: April 16, 2024Assignee: AMOREPACIFIC CORPORATIONInventors: Joon Ho Choi, Won Kyung Cho, Kwang-Hyun Shin, Byoung Young Woo, Ki-Wha Lee, Min-Soo Kim, Jong Hwa Roh, Mi Young Park, Young-Ho Park, Eun Sil Park, Jae Hong Park
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Patent number: 11947104Abstract: A spiral phase plate, according to one embodiment, for generating a Laguerre Gaussian beam by reflecting an incident beam emitted from a light source, may comprise: a first quadrant area in which the step height increase rate per unit angle decreases progressively in one direction from the point with the lowest step height to the point with the highest step height; and a second quadrant area in which the step height increase rate per unit angle increases progressively in the one direction.Type: GrantFiled: September 9, 2020Date of Patent: April 2, 2024Assignees: KOREA BASIC SCIENCE INSTITUTE, INSTITUTE FOR BASIC SCIENCE, GWANGJU INSTITUTE OF SCIENCE AND TECHNOLOGYInventors: I Jong Kim, Ji Yong Bae, Hong Seung Kim, Geon Hee Kim, Ki Soo Chang, Cheonha Jeon, Il Woo Choi, Chang Hee Nam
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Patent number: 11296088Abstract: Disclosed are a semiconductor device capable of reducing parasitic capacitance between adjacent conductive structures and a method for fabricating the same. The semiconductor device includes a plurality of bit line structures each comprising a first contact plug formed over a substrate and a bit line formed over the first contact plug. A spacer structure having air gaps is formed on sidewalls of the first contact plug and on sidewalls of the bit line. An plug isolation layer is formed between the plurality of bit line structures. The isolation layer includes an opening. A second contact plug is formed in the opening and a memory element is formed over the second contact plug.Type: GrantFiled: July 24, 2019Date of Patent: April 5, 2022Assignee: SK hynix Inc.Inventors: Chang-Youn Hwang, Noh-Jung Kwak, Hong-Gu Yi, Yun-Je Choi, Se-Han Kwon, Ki-Soo Choi, Seung-Bum Kim, Do-Hyung Kim, Doo-Sung Jung, Dae-Sik Park
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Publication number: 20190348418Abstract: Disclosed are a semiconductor device capable of reducing parasitic capacitance between adjacent conductive structures and a method for fabricating the same. The semiconductor device includes a plurality of bit line structures each comprising a first contact plug formed over a substrate and a bit line formed over the first contact plug. A spacer structure having air gaps is formed on sidewalls of the first contact plug and on sidewalls of the bit line. An plug isolation layer is formed between the plurality of bit line structures. The isolation layer includes an opening. A second contact plug is formed in the opening and a memory element is formed over the second contact plug.Type: ApplicationFiled: July 24, 2019Publication date: November 14, 2019Inventors: Chang-Youn HWANG, Noh-Jung KWAK, Hong-Gu YI, Yun-Je CHOI, Se-Han KWON, Ki-Soo CHOI, Seung-Bum KIM, Do-Hyung KIM, Doo-Sung JUNG, Dae-Sik PARK
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Patent number: 10411014Abstract: Disclosed are a semiconductor device capable of reducing parasitic capacitance between adjacent conductive structures and a method for fabricating the same. The semiconductor device includes a plurality of bit line structures each comprising a first contact plug formed over a substrate and a bit line formed over the first contact plug. A spacer structure having air gaps is formed on sidewalls of the first contact plug and on sidewalls of the bit line. An plug isolation layer is formed between the plurality of bit line structures. The isolation layer includes an opening. A second contact plug is formed in the opening and a memory element is formed over the second contact plug.Type: GrantFiled: July 15, 2016Date of Patent: September 10, 2019Assignee: SK hynix Inc.Inventors: Chang-Youn Hwang, Noh-Jung Kwak, Hong-Gu Yi, Yun-Je Choi, Se-Han Kwon, Ki-Soo Choi, Seung-Bum Kim, Do-Hyung Kim, Doo-Sung Jung, Dae-Sik Park
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Publication number: 20160329337Abstract: Disclosed are a semiconductor device capable of reducing parasitic capacitance between adjacent conductive structures and a method for fabricating the same. The semiconductor device includes a plurality of bit line structures each comprising a first contact plug formed over a substrate and a bit line formed over the first contact plug. A spacer structure having air gaps is formed on sidewalls of the first contact plug and on sidewalls of the bit line. An plug isolation layer is formed between the plurality of bit line structures. The isolation layer includes an opening. A second contact plug is formed in the opening and a memory element is formed over the second contact plug.Type: ApplicationFiled: July 15, 2016Publication date: November 10, 2016Inventors: Chang-Youn HWANG, Noh-Jung KWAK, Hong-Gu YI, Yun-Je CHOI, Se-Han KWON, Ki-Soo CHOI, Seung-Bum KIM, Do-Hyung KIM, Doo-Sung JUNG, Dae-Sik PARK
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Patent number: 9425200Abstract: Disclosed are a semiconductor device capable of reducing parasitic capacitance between adjacent conductive structures and a method for fabricating the same. The semiconductor device includes a plurality of bit line structures each comprising a first contact plug formed over a substrate and a bit line formed over the first contact plug. A spacer structure having air gaps is formed on sidewalls of the first contact plug and on sidewalls of the bit line. An plug isolation layer is formed between the plurality of bit line structures. The isolation layer includes an opening. A second contact plug is formed in the opening and a memory element is formed over the second contact plug.Type: GrantFiled: October 16, 2014Date of Patent: August 23, 2016Assignee: SK Hynix Inc.Inventors: Chang-Youn Hwang, Noh-Jung Kwak, Hong-Gu Yi, Yun-Je Choi, Se-Han Kwon, Ki-Soo Choi, Seung-Bum Kim, Do-Hyung Kim, Doo-Sung Jung, Dae-Sik Park
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Patent number: 9299604Abstract: A semiconductor device according to an embodiment of the present invention includes fuse patterns spaced apart from each other by a predetermined distance over a first interlayer insulation film; a second interlayer insulation film disposed between the fuse patterns over the first interlayer insulation film; and a capping film pattern formed over the fuse patterns and the second interlayer insulation films, the capping film pattern including a slot exposing the second interlayer insulation film.Type: GrantFiled: August 12, 2014Date of Patent: March 29, 2016Assignee: SK HYNIX INC.Inventors: Jeong Youl Kim, Ki Soo Choi
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Publication number: 20150126013Abstract: Disclosed are a semiconductor device capable of reducing parasitic capacitance between adjacent conductive structures and a method for fabricating the same. The semiconductor device includes a plurality of bit line structures each comprising a first contact plug formed over a substrate and a bit line formed over the first contact plug. A spacer structure having air gaps is formed on sidewalls of the first contact plug and on sidewalls of the bit line. An plug isolation layer is formed between the plurality of bit line structures. The isolation layer includes an opening. A second contact plug is formed in the opening and a memory element is formed over the second contact plug.Type: ApplicationFiled: October 16, 2014Publication date: May 7, 2015Inventors: Chang-Youn HWANG, Noh-Jung KWAK, Hong-Gu YI, Yun-Je CHOI, Se-Han KWON, Ki-Soo CHOI, Seung-Bum KIM, Do-Hyung KIM, Doo-Sung JUNG, Dae-Sik PARK
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Publication number: 20140349474Abstract: A semiconductor device according to an embodiment of the present invention includes fuse patterns spaced apart from each other by a predetermined distance over a first interlayer insulation film; a second interlayer insulation film disposed between the fuse patterns over the first interlayer insulation film; and a capping film pattern formed over the fuse patterns and the second interlayer insulation films, the capping film pattern including a slot exposing the second interlayer insulation film.Type: ApplicationFiled: August 12, 2014Publication date: November 27, 2014Inventors: Jeong Youl KIM, Ki Soo CHOI
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Patent number: 8836077Abstract: A semiconductor device according to an embodiment of the present invention includes fuse patterns spaced apart from each other by a predetermined distance over a first interlayer insulation film; a second interlayer insulation film disposed between the fuse patterns over the first interlayer insulation film; and a capping film pattern formed over the fuse patterns and the second interlayer insulation films, the capping film pattern including a slot exposing the second interlayer insulation film.Type: GrantFiled: December 18, 2012Date of Patent: September 16, 2014Assignee: SK Hynix Inc.Inventors: Jeong Youl Kim, Ki Soo Choi
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Publication number: 20140061907Abstract: A semiconductor device includes a metal line and a metal pad formed at different integration levels of a semiconductor substrate, and an isolation layer by which the metal line and the metal pad are spaced apart from each other. The semiconductor device prevents short-circuiting between the metal pad and the metal line although the isolation layer is dislocated.Type: ApplicationFiled: July 19, 2013Publication date: March 6, 2014Applicant: SK Hynix IncInventors: Eun Hye KWAK, Ki Soo CHOI
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Publication number: 20140015094Abstract: A semiconductor device according to an embodiment of the present invention includes fuse patterns spaced apart from each other by a predetermined distance over a first interlayer insulation film; a second interlayer insulation film disposed between the fuse patterns over the first interlayer insulation film; and a capping film pattern formed over the fuse patterns and the second interlayer insulation films, the capping film pattern including a slot exposing the second interlayer insulation film.Type: ApplicationFiled: December 18, 2012Publication date: January 16, 2014Applicant: SK HYNIX INC.Inventors: Jeong Youl KIM, Ki Soo CHOI
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Patent number: 8618628Abstract: A semiconductor device and a method for manufacturing the same are disclosed. A dummy pattern is formed between a fuse pattern and a semiconductor substrate so as to prevent the semiconductor substrate from being damaged, and a buffer pattern is formed between the dummy pattern and the semiconductor substrate, so that a dummy metal pattern primarily absorbs or reflects laser energy transferred to the semiconductor substrate during the blowing of the fuse pattern, and the buffer pattern secondarily reduces stress generated between the dummy pattern and the semiconductor substrate, resulting in the prevention of a defect such as a crack.Type: GrantFiled: October 5, 2011Date of Patent: December 31, 2013Assignee: Hynix Semiconductor Inc.Inventors: Ki Soo Choi, Do Hyun Kim
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Patent number: 8487404Abstract: The present invention provides fuse patterns and a method of manufacturing the same. According to the present invention, an insulating layer and a contact plug are filled between fuse patterns which are formed to have their ends broken and are isolated from each other. In case of a fail cell, the insulating layer is broken owing a difference in an electrical bias (current or voltage) between a metal wire and the fuse patterns, and a short is generated between the fuse patterns. Accordingly, embodiments avoid damage to a semiconductor substrate associated with a conventional fuse repair method employing laser energy, and the area of a fuse box can be reduced.Type: GrantFiled: January 10, 2012Date of Patent: July 16, 2013Assignee: Hynix Semiconductor Inc.Inventor: Ki Soo Choi
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Publication number: 20120228735Abstract: The present invention provides fuse patterns and a method of manufacturing the same. According to the present invention, an insulating layer and a contact plug are filled between fuse patterns which are formed to have their ends broken and are isolated from each other. In case of a fail cell, the insulating layer is broken owing a difference in an electrical bias (current or voltage) between a metal wire and the fuse patterns, and a short is generated between the fuse patterns. Accordingly, embodiments avoid damage to a semiconductor substrate associated with a conventional fuse repair method employing laser energy, and the area of a fuse box can be reduced.Type: ApplicationFiled: January 10, 2012Publication date: September 13, 2012Applicant: Hynix Semiconductor Inc.Inventor: Ki Soo CHOI
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Publication number: 20120104617Abstract: A semiconductor device and a method for manufacturing the same are disclosed. A dummy pattern is formed between a fuse pattern and a semiconductor substrate so as to prevent the semiconductor substrate from being damaged, and a buffer pattern is formed between the dummy pattern and the semiconductor substrate, so that a dummy metal pattern primarily absorbs or reflects laser energy transferred to the semiconductor substrate during the blowing of the fuse pattern, and the buffer pattern secondarily reduces stress generated between the dummy pattern and the semiconductor substrate, resulting in the prevention of a defect such as a crack.Type: ApplicationFiled: October 5, 2011Publication date: May 3, 2012Applicant: Hynix Semiconductor Inc.Inventors: Ki Soo CHOI, Do Hyun Kim
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Patent number: 8164156Abstract: A semiconductor device comprises a fuse having a blowing region at a center part for selectively connecting different two terminals; and a dummy contact positioned under the blowing region for forming empty space by being removed together with the blowing region in a blowing process.Type: GrantFiled: December 28, 2009Date of Patent: April 24, 2012Assignee: Hynix Semicondutor Inc.Inventors: Kyu Tae Kim, Ki Soo Choi
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Publication number: 20120092370Abstract: An apparatus to provide AR includes a marker recognition unit to recognize objects in reality information, an amalgamation determining unit to determine whether the objects are amalgamated, an amalgamation processing unit to determine an attribute of each of the recognized objects and to generate an amalgamated object based on the determined attributes, and an object processing unit to map the amalgamated object to the reality information and to display the mapped amalgamated object. A method for amalgamating objects in AR includes recognizing objects in reality information, determining whether the objects are amalgamated, determining an attribute of each of the recognized objects, generating an amalgamated object based on the determined attribute, mapping the amalgamated object to the reality information, and displaying the mapped amalgamated object.Type: ApplicationFiled: August 2, 2011Publication date: April 19, 2012Applicant: PANTECH CO., LTD.Inventors: Ik Sung OH, Dae Heum KIM, Seong Il KIM, Chan Joo PARK, Jong Hyuk EUN, Eun Mi RHEE, Kyeong Min CHOI, Ki Soo CHOI
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Publication number: 20110156257Abstract: A method for manufacturing a semiconductor device includes providing a substrate including pattern formed over the substrate and a first insulating layer formed over the pattern. A diffusion barrier layer is formed over the first insulation layer. A second insulating layer is formed over the diffusion barrier layer. The second insulating layer, the diffusion layer, and the first insulating layer are patterned to form a trench exposing the pattern. A metal layer is formed over the second insulating layer and within the trench to define a metal interconnection pattern coupling the pattern within the trench, the metal particles from the metal layer diffuse into the second insulating layer. The second insulation layer and the metal particles that have been diffused therein are removed.Type: ApplicationFiled: July 26, 2010Publication date: June 30, 2011Applicant: Hynix Semiconductor Inc.Inventor: Ki Soo CHOI