Abstract: A semiconductor memory apparatus may include: a memory cell array; an ECC (Error Check and Correction) circuit configured to detect an error from data read from the memory cell array in response to a read command, correct the detected error, and output an error correction signal whenever an error is corrected; and an EF (Error Flag) generator configured to enter a flag output mode when the number of times that the error correction signal is generated during a monitoring period reaches a threshold, and output the error correction signal as an error flag in the flag output mode.

Abstract: A semiconductor memory apparatus may include: a memory cell array; an ECC (Error Check and Correction) circuit configured to detect an error from data read from the memory cell array in response to a read command, correct the detected error, and output an error correction signal whenever an error is corrected; and an EF (Error Flag) generator configured to enter a flag output mode when the number of times that the error correction signal is generated during a monitoring period reaches a threshold, and output the error correction signal as an error flag in the flag output mode.

Abstract: A touch sensor including a sensor array including a first touch node and a second touch node adjacent to each other in at least one of a first direction or a second direction, the second direction perpendicular to the first direction, the first touch node and the second touch node electrically separated from each other, each of the first touch node and the second touch node including a driving electrode and a sensing electrode, and a controller configured to output a first driving signal having a first phase to the driving electrode of the first touch node and output a second driving signal having a second phase opposite to the first phase of the first driving signal to the driving electrode of the second touch node may be provided. The controller may be further configured to output the first driving signal and the second driving signal simultaneously.

Abstract: A memory system comprises: a memory cell array suitable for storing first data and a first parity, which is used to correct an error of the first data; and an error correcting circuit suitable for generating second data and a second parity, which includes bits obtained by correcting an error of the first parity and a bit obtained by correcting an error of a second sub-parity; wherein the error correcting circuit includes: a single error correction and double error detection (SECDED) parity generator suitable for generating a second pre-parity, which includes a first sub-parity and the second sub-parity; a syndrome decoder suitable for generating a first parity error flag and a first data error flag by decoding a syndrome; a SEC parity corrector suitable for correcting an error of the first parity based on the first parity error flag; a DED parity error detector suitable for generating a second sub-parity error flag based on an error information of the first data used to generate the second sub-parity; and a D

Abstract: A touch sensor including a sensor array including a first touch node and a second touch node adjacent to each other in at least one of a first direction or a second direction, the second direction perpendicular to the first direction, the first touch node and the second touch node electrically separated from each other, each of the first touch node and the second touch node including a driving electrode and a sensing electrode, and a controller configured to output a first driving signal having a first phase to the driving electrode of the first touch node and output a second driving signal having a second phase opposite to the first phase of the first driving signal to the driving electrode of the second touch node may be provided. The controller may be further configured to output the first driving signal and the second driving signal simultaneously.

Abstract: A semiconductor package includes a first semiconductor chip and a second semiconductor chip. The first semiconductor chip has a first pad region located at a first region of the first semiconductor chip and a second pad region located at a second region of the first semiconductor chip. The second semiconductor chip has a third pad region located at a first region of the second semiconductor chip and a fourth pad region located at a second region of the second semiconductor chip. The second semiconductor chip is stacked on the first semiconductor chip to be offset in a first lateral direction relative to the first semiconductor chip.

Abstract: A memory system comprises: a memory cell array suitable for storing first data and a first parity, which is used to correct an error of the first data; and an error correcting circuit suitable for generating second data and a second parity, which includes bits obtained by correcting an error of the first parity and a bit obtained by correcting an error of a second sub-parity; wherein the error correcting circuit includes: a single error correction and double error detection (SECDED) parity generator suitable for generating a second pre-parity, which includes a first sub-parity and the second sub-parity; a syndrome decoder suitable for generating a first parity error flag and a first data error flag by decoding a syndrome; a SEC parity corrector suitable for correcting an error of the first parity based on the first parity error flag; a DED parity error detector suitable for generating a second sub-parity error flag based on an error information of the first data used to generate the second sub-parity; and a D

Abstract: A semiconductor apparatus includes first and second chips sharing first and second data channels. The first chip compresses first test data of the first chip and outputs the compressed first test data through the first data channel in a first test mode, and the second chip compresses second test data of the second chip and outputs the compressed second test data through the second data channel in the first test mode.

Abstract: A semiconductor memory in accordance with an embodiment includes: a control unit configured to generate a plurality of second control signals in response to a page size signal and a plurality of first control signals; a plurality of input/output switches configured to be coupled to each of a plurality of unit memory blocks and activated in response to the plurality of second control signals; and a plurality of page change switches configured to couple data lines of the plurality of unit memory blocks in response to the page size signal.

Abstract: A test circuit of a semiconductor apparatus includes a plurality of pads, a pattern generator configured to generate at least one internal test pattern in response to at least one pattern select signal, and a plurality of test units configured to transmit the at least one internal test pattern through the plurality of pads in response to a self test mode signal, and to compare the at least one test pattern received via the plurality of pads with the at least one generated internal test pattern and generate at least one test determination value based on the comparison.

Abstract: A semiconductor package may include a probe circuit unit configured to be driven by buffering a signal received from a probe pad during probe testing, a bump circuit unit configured to buffer a signal received from a bump pad, and a power-source selection unit configured to change a level of an internal power-supply voltage applied to the probe circuit unit in response to a test-mode signal.

Abstract: A semiconductor apparatus includes: an output timing test unit configured to edge-trigger a pad output data applied from an input/output pad at a first timing and output the edge-triggered pad output data as output timing test data, during an output timing test mode, and a test output unit configured to receive the output timing test data and output the received output timing test data to a probe pad.

Abstract: A semiconductor apparatus includes first and second chips sharing first and second data channels. The first chip compresses first test data of the first chip and outputs the compressed first test data through the first data channel in a first test mode, and the second chip compresses second test data of the second chip and outputs the compressed second test data through the second data channel in the first test mode.

Abstract: A semiconductor apparatus includes first and second chips sharing first and second data channels. The first chip compresses first test data of the first chip and outputs the compressed first test data through the first data channel in a first test mode, and the second chip compresses second test data of the second chip and outputs the compressed second test data through the second data channel in the first test mode.

Abstract: A test circuit of a semiconductor apparatus includes a plurality of pads, a pattern generator configured to generate at least one internal test pattern in response to at least one pattern select signal, and a plurality of test units configured to transmit the at least one internal test pattern through the plurality of pads in response to a self test mode signal, and to compare the at least one test pattern received via the plurality of pads with the at least one generated internal test pattern and generate at least one test determination value based on the comparison.

Abstract: A semiconductor integrated circuit includes an input data line pair, a sense amplifier configured to sense and amplify data loaded in the input data line pair and transmit the amplified data to an output data line pair, in response to a control signal, and a sense amplification controller configured to sense an amplification level of the output data line pair, limit an activation period of a sense amplification enable signal, and output the limited signal as the control signal.

Abstract: A semiconductor memory in accordance with an embodiment includes: a control unit configured to generate a plurality of second control signals in response to a page size signal and a plurality of first control signals; a plurality of input/output switches configured to be coupled to each of a plurality of unit memory blocks and activated in response to the plurality of second control signals; and a plurality of page change switches configured to couple data lines of the plurality of unit memory blocks in response to the page size signal.

Abstract: A semiconductor apparatus includes: an output timing test unit configured to edge-trigger a pad output data applied from an input/output pad at a first timing and output the edge-triggered pad output data as output timing test data, during an output timing test mode, and a test output unit configured to receive the output timing test data and output the received output timing test data to a probe pad.

Abstract: A semiconductor integrated circuit includes an input data line pair, a sense amplifier configured to sense and amplify data loaded in the input data line pair and transmit the amplified data to an output data line pair, in response to a control signal, and a sense amplification controller configured to sense an amplification level of the output data line pair, limit an activation period of a sense amplification enable signal, and output the limited signal as the control signal.

Abstract: A semiconductor apparatus includes first and second chips sharing first and second data channels. The first chip compresses first test data of the first chip and outputs the compressed first test data through the first data channel in a first test mode, and the second chip compresses second test data of the second chip and outputs the compressed second test data through the second data channel in the first test mode.