Abstract: A semiconductor integrated circuit includes a pre driver unit configured to receive a pre drive signal and a driving force control signal and output a main drive signal; a main driver unit configured to receive the main drive signal and output output data to an output terminal; a terminal connecting unit configured to receive a determination signal and connect to or disconnect from the output terminal in response to the determination signal; a terminal sensing unit configured to sense the output terminal and output a terminal state signal; and a driving force determining unit configured to receive a reset signal and the terminal state signal and output the driving force control signal.

Abstract: A semiconductor integrated circuit includes a pre driver unit configured to receive a pre drive signal and a driving force control signal and output a main drive signal; a main driver unit configured to receive the main drive signal and output output data to an output terminal; a terminal connecting unit configured to receive a determination signal and connect to or disconnect from the output terminal in response to the determination signal; a terminal sensing unit configured to sense the output terminal and output a terminal state signal; and a driving force determining unit configured to receive a reset signal and the terminal state signal and output the driving force control signal.

Abstract: A fuse set of a semiconductor memory includes a first fuse array and a second fuse array each configured to designate a column redundancy address; and a unit fuse circuit configured to select one of the first fuse array and the second fuse array based on a row address.

Abstract: A test mode signal generator for a semiconductor memory device includes a test mode entry control unit that receives test entry mode setting addresses inputted in response to a test mode register set signal. The test mode entry control unit outputs a plurality of test entry mode signals and a test mode set signal according to the test entry mode setting addresses. A latch unit latches test address decoding signals in response to the test mode set signal, and outputs test mode signals by allowing the latched test address decoding signals to be controlled by the respective test entry mode signals. A test mode signal is generated for each test entry mode, so that the number of test modes is increased without increasing the number of addresses for supporting test modes.

Abstract: A termination control circuit for a global input/output line includes a speed determination unit configured to output a termination enable signal which is activated in response to a frequency of an external clock signal and CAS latency information; and a pulse generation unit configured to output a driving signal for driving a termination circuit for the global input/output line in response to a termination control signal and the termination enable signal.

Abstract: A termination control circuit for a global input/output line includes a speed determination unit configured to output a termination enable signal which is activated in response to a frequency of an external clock signal and CAS latency information; and a pulse generation unit configured to output a driving signal for driving a termination circuit for the global input/output line in response to a termination control signal and the termination enable signal.

Abstract: A test mode signal generator for a semiconductor memory device includes a test mode entry control unit that receives test entry mode setting addresses inputted in response to a test mode register set signal. The test mode entry control unit outputs a plurality of test entry mode signals and a test mode set signal according to the test entry mode setting addresses. A latch unit latches test address decoding signals in response to the test mode set signal, and outputs test mode signals by allowing the latched test address decoding signals to be controlled by the respective test entry mode signals. A test mode signal is generated for each test entry mode, so that the number of test modes is increased without increasing the number of addresses for supporting test modes.