Patents by Inventor Ki Won Lee

Ki Won Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11026615
    Abstract: Provided is a dry electrode for detecting a bio-signal, comprising a body part; a protrusion part formed on one surface of the body part; and a coating part formed on an end surface of the protrusion part, wherein the body part and the protrusion part comprise a conductive silicone, and the coating part comprises Ag, AgCl, and, optionally, 3-aminopropyltriethoxysilane.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: June 8, 2021
    Assignee: Y-BRAIN INC
    Inventors: Ki-Won Lee, Cheon-Ju Ko, Jong-Min Jang, Byung-Gik Kim
  • Patent number: 11032814
    Abstract: A User Equipment (UE) monitors a set of Physical Downlink Control Channel (PDCCH) candidates for control information received from a base station at subframe k. The set of PDCCH candidates to monitor are defined in terms of search spaces. The UE monitors a UE-specific search space, among the search spaces, at each of aggregation levels (L) of 1, 2, 4 and 8 control channel elements (CCEs), the CCE being a resource unit comprising a specific number of resource elements and used for transmission of the control information. The L CCEs correspond to a first PDCCH candidate among the set of PDCCH candidates of the search space at a subframe k are located at positions given by: L*{(Yk)mod(floor(C))}+i, wherein i?0, . . . , L?1, where Yk is defined by: Yk?(A*Yk?1+B) mod D. The variable C is determined based on the number of CCEs (NCCE) divided by the aggregation level (L), and A, B, and D are predetermined constant values predetermined regardless of the aggregation levels L.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: June 8, 2021
    Assignee: Optis Cellular Technology, LLC
    Inventors: Dae Won Lee, Ki Jun Kim, Dong Wook Roh, Yu Jin Noh, Joon Kui Ahn, Jung Hoon Lee
  • Patent number: 11028629
    Abstract: A door glass assembly is configured to reduce an impact noise generated when a door glass is moved upward/downward and may include a carrier plate coupled to a glass holder to which a door glass of a vehicle is secured. The carrier plate is installed inside a door of the vehicle so as to be movable upward/downward. A module plate, on which the carrier plate is installed so as to be movable upward/downward, is installed inside the door of the vehicle. A driving motor is provided to move the carrier plate upward/downward. The module plate and the carrier plate are provided with an impact noise preventing means for gradually decelerating and stopping the carrier plate when the door glass is being maximally moved upward or downward.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: June 8, 2021
    Assignees: HYUNDAI MOTOR COMPANY, KIA MOTORS CORPORATION
    Inventors: Seok-Hyun Hong, Kwan-Hui Kang, Kuk-Hoon Lee, Soo-Bok Kim, Hee-Won Kang, Hoon-Ju Jo, Jun-Hee An, Ki-Su Kim, Nam-Hee Yun
  • Patent number: 11031077
    Abstract: A resistance variable memory device may include a plurality of memory cells and a control circuit block. The memory cells may be connected between a global word line and a global bit line. The control circuit block may control the memory cells. The control circuit block may include a write pulse control block. The write pulse control block may include a high resistance path circuit and a bypass circuit connected between the global word line and a selected memory cell. The write pulse control block may selectively enable any one of the high resistance path circuit and the bypass circuit in accordance with a position the selected memory cell.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: June 8, 2021
    Assignee: SK hynix Inc.
    Inventors: Ki Won Lee, Jin Su Park
  • Publication number: 20210166791
    Abstract: An apparatus for constructing a library for deriving a material composition using empirical result, which enables acceleration of research on the material-properties relationship. By applying the empirical results of the material composition, missing data of the material compositions can be statistically calculated by using supervised non-linear imputation techniques. The completed composition information of the materials is passed as an input of machine learning material-properties relationship prediction.
    Type: Application
    Filed: December 18, 2019
    Publication date: June 3, 2021
    Inventors: Seung Bum HONG, Eun Ae CHO, Jong Min YUK, Hye Ryung BYON, Yong Soo YANG, Pyuck Pa CHOI, Jong Hwa SHIN, Hyuck Mo LEE, CHI HAO LIOW, Seong Woo CHO, Gun PARK, Yong Ju LEE, Yoon Su SHIM, Moo Ny NA, Ho Sun JUN, Ki Hoon BANG, Myung Joon KIM, Chae Hwa JEONG, Seung Gu KIM, Chung Ik OH, Hong Jun KIM, Jae Gyu KIM, Ji Min OH, Ji Won YEOM, Seong Mun EOM, Hyoung Kyu KIM, Young Joon HAN, Dae Hee LEE, Ho Jun LEE, Jae Woon KIM, Jae Wook SHIN, Hyeon Muk KANG, Jae Yeol PARK, Han Beom JEONG, Jae Sang LEE, Joon Ha CHANG, Yo Han KIM, Su Jung KIM, Hyun Jeong OH, Arthur Baucour, Jae Wook HAN, Kyu Seon JANG, Hye Sung JO, Bo Ryung YOO, Hyeon Jin PARK, Min Gwan CHO, Jun Hyung PARK, Yea Eun KIM, Seok Hwan MIN, Jung Woo CHOI, Young Tae PARK, Doo Sun HONG
  • Patent number: 11012222
    Abstract: A method for transmitting uplink signals, which include ACK/NACK signals, control signals other than the ACK/NACK signals, and data signals, is disclosed. The method comprises serially multiplexing the control signals and the data signals; sequentially mapping the multiplexed signals within a specific resource region in accordance with a time-first mapping method, the specific resource region including a plurality of symbols and a plurality of virtual subcarriers; and arranging the ACK/NACK signals at both symbols near symbols to which a reference signal of the plurality of symbols is transmitted. Thus, the uplink signals can be transmitted to improve receiving reliability of signals having high priority.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: May 18, 2021
    Assignee: Optis Cellular Technology, LLC
    Inventors: Dae Won Lee, Bong Hoe Kim, Young Woo Yun, Ki Jun Kim, Dong Wook Roh, Hak Seong Kim, Hyun Wook Park
  • Publication number: 20210140027
    Abstract: Provided are a refractory article, an anti-redox coating composition, and a method of manufacturing the refractory article. The refractory article includes: a platinum (Pt)-based substrate; and a coating layer for preventing a redox reaction on a surface of the Pt-based substrate, wherein the coating layer for preventing a redox reaction includes on an oxide basis SiO2 in an amount of about 40 wt % to about 70 wt %, Al2O3 in an amount of about 20 wt % to about 52 wt %, B2O3 in an amount of about 3 wt % to about 6 wt %; and CaO in an amount of about 2.4 wt % to about 4.8 wt %.
    Type: Application
    Filed: June 18, 2018
    Publication date: May 13, 2021
    Inventors: Myeong-jin Cho, Hong-goo Choi, Soon-yong Choi, Ki-ju Kwak, Yong-won Lee, Yun-Kyung Sung
  • Publication number: 20210143187
    Abstract: A substrate including a gate line and a first electrode disposed on the substrate, an oxide semiconductor layer pattern overlapping the first electrode, an insulating layer disposed between the first electrode and the oxide semiconductor layer pattern, a data line intersecting the gate line, a second electrode electrically connected to the oxide semiconductor layer pattern, a third electrode electrically connected to the oxide semiconductor layer, the third electrode spaced apart from the second electrode, and an insulating pattern including a first portion which is disposed between the gate line and the data line and at least partially overlaps with both of the gate line and the data line.
    Type: Application
    Filed: December 17, 2020
    Publication date: May 13, 2021
    Inventors: Young-Wook LEE, Woo-Geun LEE, Ki-Won KIM, Hyun-Jung LEE, Ji-Soo OH
  • Patent number: 11003293
    Abstract: An electronic device and method are disclosed. The electronic device includes a memory, a display, a touch sensor included in the display or coupled to the display, and configured to sense a touch. A pressure sensor configured to detect a pressure value of the touch and a processor electrically connected with the memory, the display, the touch sensor, and the pressure sensor, wherein the processor is configured to sense a first touch having a pressure value of a specified threshold value or greater, by using the touch sensor and the pressure sensor, store first location data of the first touch in the memory, sense a second touch, by using the touch sensor and the pressure sensor, wherein the second touch has a pressure value of the specified threshold value or greater and is made after sensing the first touch and perform a specified operation of utilizing the first location data and second location data of the second touch as an input, in response to sensing the second touch.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: May 11, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Mee Ryung Choi, Keun Sik Lee, Hye Won Im, Moo Young Kim, Ki Huk Lee, Seung Won Cha, Ho Chul Hwang
  • Publication number: 20210134941
    Abstract: A stacked structure including: a single crystal substrate and, single crystal material on the single crystal substrate, wherein the single crystal material has a same crystallographic orientation as a crystallographic orientation of the single crystal substrate. Also a method of forming the stacked structure, a ceramic electronic component, and a device.
    Type: Application
    Filed: January 14, 2021
    Publication date: May 6, 2021
    Inventors: Hyungjun KIM, Doh Won JUNG, Chan KWAK, Ki Hong KIM, Daejin YANG, Chang Soo LEE
  • Publication number: 20210132351
    Abstract: Provided are a device for analyzing a large-area sample based on an image, a device for analyzing a sample based on an image by using a difference in medium characteristic, and a method for measuring and analyzing a sample by using the same. The device for analyzing a large-area sample includes a first sensor array including a plurality of sensors which are disposed while being spaced apart from each other in a first direction, a second sensor array including a plurality of sensors, which are disposed while being spaced apart from each other in the first direction, and spaced apart from the first sensor array in a second direction, and a control unit to obtain image data for a cell included in the sample by using sensing data of the sensor on the sample, in which the sample is interposed between the first sensor array and the second sensor array. An active area of one of the sensor in the first sensor array overlaps an active area of one of the sensors in the second sensor array, in the second direction.
    Type: Application
    Filed: November 28, 2020
    Publication date: May 6, 2021
    Applicant: SOL INC.
    Inventors: Jong Muk LEE, Hee Chan SHIN, Seong Won KWON, Ki Ho JANG
  • Publication number: 20210126771
    Abstract: A file transmission method includes storing each chunk of a target file by public cloud, receiving, by the first node, a file transmission request including an encrypted chunk order sheet of the target file, information on the target file and recipient information, wherein the chunk order sheet includes connection order information of each chunk necessary for restoring the target file, and the encrypted chunk order sheet is encrypted with a public key of a recipient, storing a first transaction including information included in the file transmission request and chunk storage location information in a ledger stored in the first node, storing, by the second node, the first transaction in a ledger of the second node according to synchronization of the ledger, storing a chunk in the internal storage using the chunk storage location information when the recipient information included in the first transaction includes a user belonging to the intranet.
    Type: Application
    Filed: October 29, 2019
    Publication date: April 29, 2021
    Inventors: Sang Ji BAE, Sang Jun KANG, Ki Woon SUNG, Sang Won LEE, Kyu Sang LEE
  • Publication number: 20210104277
    Abstract: A variably resistive memory device may include a memory cell array and a control circuit block. The memory cell array may include a plurality of word lines, a plurality of bit lines and a plurality of memory cells. The memory cell array may also include memory layers connected between the word lines and the bit lines. The control circuit block may include a read/write circuit and a bit line control circuit. The read/write circuit may be configured to provide a selected bit line among the plurality of bit lines with a read voltage or a write voltage. The bit line control circuit may be connected with the read/write circuit and the bit lines to control a bit line voltage inputted into the selected bit line based on a location at which a selected memory cell is electrically connected to the selected bit line.
    Type: Application
    Filed: December 16, 2020
    Publication date: April 8, 2021
    Applicant: SK hynix Inc.
    Inventors: Ki Won LEE, Jung Hyuk YOON
  • Patent number: 10964382
    Abstract: A variable resistive memory device includes a memory cell, a first circuit, and a second circuit. The memory cell is connected between a word line and a bit line. The first circuit provides the bit line with a first pulse voltage based on at least one enable signal. The second circuit provides the word line with a second pulse voltage based on the enable signal. The first circuit generates the first pulse voltage increased in steps from an initial voltage level to a target voltage level.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: March 30, 2021
    Assignee: SK hynix Inc.
    Inventors: Ki Won Lee, Seok Man Hong, Tae Hoon Kim, Hyung Dong Lee
  • Patent number: 10878903
    Abstract: A variably resistive memory device may include a memory cell array and a control circuit block. The memory cell array may include a plurality of word lines, a plurality of bit lines and a plurality of memory cells. The memory cell array may also include memory layers connected between the word lines and the bit lines. The control circuit block may include a read/write circuit and a bit line control circuit. The read/write circuit may be configured to provide a selected bit line among the plurality of bit lines with a read voltage or a write voltage. The bit line control circuit may be connected with the read/write circuit and the bit lines to control a bit line voltage inputted into the selected bit line based on a location at which a selected memory cell is electrically connected to the selected bit line.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: December 29, 2020
    Assignee: SK hynix Inc.
    Inventors: Ki Won Lee, Jung Hyuk Yoon
  • Publication number: 20200327939
    Abstract: A resistance variable memory device may include a plurality of memory cells and a control circuit block. The memory cells may be connected between a global word line and a global bit line. The control circuit block may control the memory cells. The control circuit block may include a write pulse control block. The write pulse control block may include a high resistance path circuit and a bypass circuit connected between the global word line and a selected memory cell. The write pulse control block may selectively enable any one of the high resistance path circuit and the bypass circuit in accordance with a position the selected memory cell.
    Type: Application
    Filed: December 16, 2019
    Publication date: October 15, 2020
    Applicant: SK hynix Inc.
    Inventors: Ki Won LEE, Jin Su PARK
  • Patent number: 10699760
    Abstract: A semiconductor system includes a first set of at least one semiconductor device, and a second set of at least one semiconductor device. The semiconductor system includes a control block for receiving an external address and providing the first and second sets of semiconductor devices with an internal address. The control block provides a semiconductor device from the first set with a first internal address corresponding to the external address, and the control block provides a semiconductor device from the second set with a second internal address that does not correspond to the external address.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: June 30, 2020
    Assignee: SK hynix Inc.
    Inventors: Hyuck Sang Yim, Ki Won Lee, Seoung Ju Chung
  • Publication number: 20200202998
    Abstract: Disclosed is a method for setting authority for use of a brain stimulation device and a device implementing the same, and the method for setting authority for use of a brain stimulation device according to the present disclosure comprises the steps in which: a communication unit of a personal communication device receives, from a server device, a time token for which the authority for use of the brain stimulation device is set; the communication unit transmits the time token to the brain stimulation device or the server device; and after a time corresponding to the usage time of the brain stimulation device stored in the time token has elapsed, the communication unit receives, from the brain stimulation device or the server device, a message to delete the time token or to change the value of a specific field of the time token.
    Type: Application
    Filed: August 30, 2017
    Publication date: June 25, 2020
    Inventors: Seong-Hoon KIM, Ki-Won LEE
  • Publication number: 20200082882
    Abstract: An electronic device including a semiconductor memory The semiconductor memory includes one or more resistive storage cells; at least one reference resistance block including at least two reference resistance transistors which are coupled in series; a data sensing block suitable for comparing resistance values of a resistive storage cell selected among the one or more resistive storage cells and the reference resistance block, and sensing data of the selected resistive storage cell; and a reference resistance adjustment block suitable for adjusting the resistance value of the reference resistance block by adjusting gate voltages of the reference resistance transistors.
    Type: Application
    Filed: November 15, 2019
    Publication date: March 12, 2020
    Inventor: Ki-Won Lee
  • Patent number: D898515
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: October 13, 2020
    Inventor: Ki Won Lee