Abstract: A variably resistive memory device may include a memory cell array and a control circuit block. The memory cell array may include a plurality of word lines, a plurality of bit lines and a plurality of memory cells. The memory cell array may also include memory layers connected between the word lines and the bit lines. The control circuit block may include a read/write circuit and a bit line control circuit. The read/write circuit may be configured to provide a selected bit line among the plurality of bit lines with a read voltage or a write voltage. The bit line control circuit may be connected with the read/write circuit and the bit lines to control a bit line voltage inputted into the selected bit line based on a location at which a selected memory cell is electrically connected to the selected bit line.

Abstract: A resistance variable memory device may include a plurality of memory cells and a control circuit block. The memory cells may be connected between a global word line and a global bit line. The control circuit block may control the memory cells. The control circuit block may include a write pulse control block. The write pulse control block may include a high resistance path circuit and a bypass circuit connected between the global word line and a selected memory cell. The write pulse control block may selectively enable any one of the high resistance path circuit and the bypass circuit in accordance with a position the selected memory cell.

Abstract: A semiconductor system includes a first set of at least one semiconductor device, and a second set of at least one semiconductor device. The semiconductor system includes a control block for receiving an external address and providing the first and second sets of semiconductor devices with an internal address. The control block provides a semiconductor device from the first set with a first internal address corresponding to the external address, and the control block provides a semiconductor device from the second set with a second internal address that does not correspond to the external address.

Abstract: Disclosed is a method for setting authority for use of a brain stimulation device and a device implementing the same, and the method for setting authority for use of a brain stimulation device according to the present disclosure comprises the steps in which: a communication unit of a personal communication device receives, from a server device, a time token for which the authority for use of the brain stimulation device is set; the communication unit transmits the time token to the brain stimulation device or the server device; and after a time corresponding to the usage time of the brain stimulation device stored in the time token has elapsed, the communication unit receives, from the brain stimulation device or the server device, a message to delete the time token or to change the value of a specific field of the time token.

Abstract: An electronic device including a semiconductor memory The semiconductor memory includes one or more resistive storage cells; at least one reference resistance block including at least two reference resistance transistors which are coupled in series; a data sensing block suitable for comparing resistance values of a resistive storage cell selected among the one or more resistive storage cells and the reference resistance block, and sensing data of the selected resistive storage cell; and a reference resistance adjustment block suitable for adjusting the resistance value of the reference resistance block by adjusting gate voltages of the reference resistance transistors.

Abstract: An electronic device includes a semiconductor memory. The semiconductor memory includes one or more resistive storage cells each structured to exhibit different resistance values for storing data; at least one reference resistance transistor to produce a reference resistance value; a reference resistance adjustment block coupled to the at least one reference resistance transistor and structured to supply a signal to the at least one reference resistance transistor that can cause an adjustment in the resistance value of the reference resistance transistor; and a data sensing block coupled to the one or more resistive storage cells and the at least one reference resistance transistor, the data sensing block structured to sense resistance values of a resistive storage cell selected among the one or more resistive storage cells and the at least one reference resistance transistor and to compare the sensed resistance values to determine data of the selected resistive storage cell.

Abstract: A variable resistive memory device includes a memory cell, a first circuit, and a second circuit. The memory cell is connected between a word line and a bit line. The first circuit provides the bit line with a first pulse voltage based on at least one enable signal. The second circuit provides the word line with a second pulse voltage based on the enable signal. The first circuit generates the first pulse voltage increased in steps from an initial voltage level to a target voltage level.

Abstract: An electronic device including a semiconductor memory The semiconductor memory includes one or more resistive storage cells; at least one reference resistance block including at least two reference resistance transistors which are coupled in series; a data sensing block suitable for comparing resistance values of a resistive storage cell selected among the one or more resistive storage cells and the reference resistance block, and sensing data of the selected resistive storage cell; and a reference resistance adjustment block suitable for adjusting the resistance value of the reference resistance block by adjusting gate voltages of the reference resistance transistors.

Abstract: A semiconductor system includes a first set of at least one semiconductor device, and a second set of at least one semiconductor device. The semiconductor system includes a control block for receiving an external address and providing the first and second sets of semiconductor devices with an internal address. The control block provides a semiconductor device from the first set with a first internal address corresponding to the external address, and the control block provides a semiconductor device from the second set with a second internal address that does not correspond to the external address.

Abstract: An embodiment of the present invention discloses an exercise measuring device attachable to and detachable from a bar of an exercise apparatus, the exercise measuring device including: a main body; a coupling portion formed on the main body and configured to be coupled to at least an end portion of the bar; and a reader formed on the main body, wherein when a weight portion including a tag is fitted to the end portion of the bar, the reader detects a weight of the weight portion fitted to the bar by reading the tag of the weight portion.

Abstract: Provided is an electrical stimulation device. The electrical stimulation device includes a first electrode that contacts a first portion of the head of a user to apply a current to the head of the user, a second electrode that contacts a second portion that is different from the first portion of the head of the user to apply a current to the head of the user, a controller that performs a control such that polarities of the first electrode and the second electrode can be changed based on a reference comprising at least one of a reference time, a reference pH index, and a reference number of uses.

Abstract: An electrical stimulation and bio-potential measurement device is provided. The electrical stimulation and bio-potential measurement device comprises at least one electrode module which comes into contact with the scalp of a user, a current supply unit, connected to the at least one electrode module, for supplying a current to the at least one electrode module so that the at least one electrode module can apply electrical stimulation to the user, and a signal processing unit, connected to the at least one electrode module, for processing bio-potential signals detected by the at least one electrode module, wherein the current supply unit comprises at least one switch which is arranged between the at least one electrode module and a voltage source for supplying the current.

Abstract: An electrical stimulation apparatus is provided. The electrical stimulation apparatus includes a frame worn on a user, an electrode module including a plurality of microelectrodes covered by a single patch, one surface of the electrode module is connected to the frame and the other surface faces the user while being covered by the single patch, and a processor controlling an operation of the electrode module such that a target effect is capable of being provided to the user through electrical stimulation in a state where the frame is worn on the user.

Abstract: An electrical stimulation apparatus is provided. The electrical stimulation apparatus includes an electrode module receiving current for applying electrical stimulation to a skin of a user from a current providing part, a plurality of monitoring electrodes positioned spaced apart from each other on the electrode module, the current flows from the electrode module to the plurality of monitoring electrodes, and a current monitoring part monitoring the current flowing to each of the plurality of monitoring electrodes.

Abstract: A variably resistive memory device may include a memory cell array and a control circuit block. The memory cell array may include a plurality of word lines, a plurality of bit lines and a plurality of memory cells. The memory cell array may also include memory layers connected between the word lines and the bit lines. The control circuit block may include a read/write circuit and a bit line control circuit. The read/write circuit may be configured to provide a selected bit line among the plurality of bit lines with a read voltage or a write voltage. The bit line control circuit may be connected with the read/write circuit and the bit lines to control a bit line voltage inputted into the selected bit line based on a location at which a selected memory cell is electrically connected to the selected bit line.

Abstract: A data processing system includes a host device; and a data storage device suitable for detecting a voltage drop state in the voltage received from the host device, changing a first key received from the host device to a second key when detecting the voltage drop state, generating a cyclical redundancy check (CRC) data based on the second key, and transmitting the generated CRC data to the host device.

Abstract: A transcranial direct current stimulation (tDCS) apparatus includes a stimulation unit, a control unit, and an input/output (I/O) unit. The stimulation unit includes a power-supply unit to supply power for electrical stimulation corresponding to a control signal received from the control unit, and a plurality of stimulation electrodes, each of which has a hydrogel patch, to provide electrical stimulation to a living body upon receiving the power from the power-supply unit. The control unit is configured to control an on/off function of the power-supply unit such that the power-supply unit is turned on or off according to the amount of power applied to the stimulation electrodes and a time period during which the power is supplied or not supplied.

Abstract: A semiconductor device may be provided. The semiconductor device may include a first input signal-inverting circuit, a second input signal-inverting circuit, a first level-shifting circuit and a second level-shifting circuit. The first input signal-inverting circuit may be configured to invert and output an input signal. The second input signal-inverting circuit may be configured to invert and output an output signal from the first input signal-inverting circuit. The first level-shifting circuit may be configured to determine a voltage level of a first output node in response to the output signals from the first and second input signal-inverting circuits. The second level-shifting circuit may be configured to determine a voltage level of a second output node in response to the output signals from the first and second input signal-inverting circuits.

Abstract: A method and device for searching for a network in a wireless communication environment supporting a plurality of communication methods are provided. An example method to support Simultaneous Voice and LTE (SVLTE) and Circuit Switch-FallBack (CSFB) involves determining a communication mode when a booting or rebooting event or no-data service event occurs, and only searching for a signal related to a selected one of the communication modes, thereby reducing total scan time needed to access a network.