Patents by Inventor Kian Chai Lee

Kian Chai Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030164550
    Abstract: An electronic device package having semiconductor die-carrying interposer substrates in a stacked configuration. Each interposer substrate bears at least one die mounted by its active surface to a surface of the interposer substrate and wire bonded to terminals on the opposing substrate surface through an opening in the interposer substrate. Two interposer substrates are placed together with die-carrying sides outward and electrically connected with conductive elements extending transversely therebetween to form an interposer assembly, the interposer assembly bearing conductive elements extending transversely from one of the interposer substrates for connection to a carrier substrate. The space between the interposer substrates may be filled with a dielectric underfill material, as may the space between the interposer assembly and the carrier substrate to which the former is mounted.
    Type: Application
    Filed: March 12, 2003
    Publication date: September 4, 2003
    Inventors: Teck Kheng Lee, Kian Chai Lee
  • Publication number: 20030164551
    Abstract: A method and apparatus for increasing the integrated circuit density in a flip chip semiconductor device assembly including an interposer substrate facilitating use with various semiconductor die conductive bump arrangements. The interposer substrate includes a plurality of recesses formed in at least one of a first surface and a second surface of the interposer substrate, wherein the recesses are arranged in a plurality of recess patterns. The interposer substrate also provides enhanced accessibility for test probes for electrical testing of the resulting flip chip semiconductor device assembly.
    Type: Application
    Filed: May 17, 2002
    Publication date: September 4, 2003
    Inventors: Teck Kheng Lee, Wuu Yean Tay, Kian Chai Lee
  • Publication number: 20030148557
    Abstract: Semiconductor die units for forming BOC BGA packages, methods of encapsulating a semiconductor die unit, a mold for use in the method, and resulting encapsulated packages are provided. In particular, the invention provides a semiconductor die unit comprising an integrated circuit die with a plurality of bond pads in an I-shaped layout and an overlying support substrate having an I-shaped wire bond slot.
    Type: Application
    Filed: February 5, 2002
    Publication date: August 7, 2003
    Inventors: Thiam Chye Lim, Kay Kit Tan, Kian Chai Lee, Victor Cher Khng Tan, Kwang Hong Tan, Chong Pei Andrew Lim, Yong Kian Tan, Teck Kheng Lee, Sian Yong Khoo, Yoke Kuin Tang
  • Patent number: 6583502
    Abstract: A method and apparatus for assembling semiconductor die-carrying interposer substrates in a stacked configuration. Each interposer substrate bears at least one die mounted by its active surface to a surface of the substrate and wire bonded to terminals on the opposing substrate surface through an opening in the substrate. Two interposer substrates are placed together with die carrying sides outward and electrically connected with conductive elements extending transversely therebetween to form an interposer assembly, the interposer assembly bearing conductive elements extending transversely from one of the interposer substrates for connection to a carrier substrate. The space between the interposer substrates may be filled with a dielectric underfill material, as may the space between the interposer assembly and the carrier substrate to which the former is mounted.
    Type: Grant
    Filed: June 5, 2001
    Date of Patent: June 24, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Teck Kheng Lee, Kian Chai Lee
  • Publication number: 20030102546
    Abstract: A method and apparatus for assembling semiconductor die-carrying interposer substrates in a stacked configuration. Each interposer substrate bears at least one die mounted by its active surface to a surface of the interposer substrate and wire bonded to terminals on the opposing substrate surface through an opening in the interposer substrate. Two interposer substrates are placed together with die-carrying sides outward and electrically connected with conductive elements extending transversely therebetween to form an interposer assembly, the interposer assembly bearing conductive elements extending transversely from one of the interposer substrates for connection to a carrier substrate. The space between the interposer substrates may be filled with a dielectric underfill material, as may the space between the interposer assembly and the carrier substrate to which the former is mounted.
    Type: Application
    Filed: December 31, 2002
    Publication date: June 5, 2003
    Inventors: Teck Kheng Lee, Kian Chai Lee
  • Publication number: 20020149097
    Abstract: A method and apparatus for assembling semiconductor die-carrying interposer substrates in a stacked configuration. Each interposer substrate bears at least one die mounted by its active surface to a surface of the substrate and wire bonded to terminals on the opposing substrate surface through an opening in the substrate. Two interposer substrates are placed together with die carrying sides outward and electrically connected with conductive elements extending transversely therebetween to form an interposer assembly, the interposer assembly bearing conductive elements extending transversely from one of the interposer substrates for connection to a carrier substrate. The space between the interposer substrates may be filled with a dielectric underfill material, as may the space between the interposer assembly and the carrier substrate to which the former is mounted.
    Type: Application
    Filed: June 5, 2001
    Publication date: October 17, 2002
    Inventors: Teck Kheng Lee, Kian Chai Lee
  • Publication number: 20020072153
    Abstract: A method and apparatus for distributing a mold material in a mold for packaging microelectronic devices. In one embodiment, the microelectronic devices are placed on a substrate and the substrate is at least partially enclosed by the device region of a mold cavity. A mold material is passed along a flow axis through at least one entrance port into an intermediate region of the mold. The mold material is then passed from the intermediate region into the device region through a single opening spaced apart from and positioned between the entrance port and the microelectronic device. The single opening has a flow area transverse to the flow axis smaller than a flow area immediately upstream of the single opening to restrict the flow through the single opening. The mold material can accordingly form a uniform leading edge as it exits the opening and before it impinges on the microelectronic device.
    Type: Application
    Filed: May 8, 2001
    Publication date: June 13, 2002
    Inventors: Kian Chai Lee, Teoh Bee Yong Tim, M. Vijendran, Lien Wah Choong