Abstract: A semiconductor package and a manufacturing method thereof are provided. The package element has a first insulating layer, and a plurality of holes are disposed on the first surface of the first insulating layer. Besides, a plurality of package traces are embedded in the insulating layer and connected to the other end of the holes. The holes function as a positioning setting for connecting the solder balls to the package traces, such that the signal of the semiconductor chip is connected to the package trace via conductor of the chip, and further transmitted externally via solder ball. The elastic modulus of the material of the first insulating layer is preferably larger than 1.0 GPa.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device has an active surface. The semiconductor device includes at least a connecting element and at least a bump. The connecting element is disposed on the activate surface and has a minimum dimension smaller than 100 microns. The bump is disposed on the connecting element and is electrically connected to the active surface by the connecting element. The bump includes a pillar part disposed on the connecting element and a top part disposed at the top of the pillar part. The pillar part has a first dimension and a second dimension both parallel to the active surface. The first dimension is longer than 1.2 times the second dimension. The top part is composed of solder and will melt under the determined temperature. The pillar part will not melt under a determined temperature.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The package element has a first insulating layer, and a plurality of holes are disposed on the first surface of the first insulating layer. Besides, a plurality of package traces are embedded in the insulating layer and connected to the other end of the holes. The holes function as a positioning setting for connecting the solder balls to the package traces, such that the signal of the semiconductor chip is connected to the package trace via conductor of the chip, and further transmitted externally via solder ball. The elastic modulus of the material of the first insulating layer is preferably larger than 1.0 GPa.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device has an active surface. The semiconductor device includes at least a connecting element and at least a bump. The connecting element is disposed on the activate surface and has a minimum dimension smaller than 100 microns. The bump is disposed on the connecting element and is electrically connected to the active surface by the connecting element. The bump includes a pillar part disposed on the connecting element and a top part disposed at the top of the pillar part. The pillar part has a first dimension and a second dimension both parallel to the active surface. The first dimension is longer than 1.2 times the second dimension. The top part is composed of solder and will melt under the determined temperature. The pillar part will not melt under a determined temperature.

Abstract: A semiconductor element that includes a forsy patterned conductive layer, a second pattern conductive layer and an insulating layer. The first surface of the second patterned conductive layer is connected to a second surface of the first patterned conductive layer. The insulating layer includes at least one space on a second surface thereof. The first patterned conductive layer and the second patterned conductive layer are embedded in the insulating layer between a first surface and a second surface thereof, the first surface of the first patterned conductive layer is entirely exposed on a first surface of the insulating layer, a second surface of the second patterned conductive layer is entirely exposed on the second surface of the insulating layer, and the space exposes the second surface of the first patterned conductive layer.

Abstract: A method for fabricating a flip-chip semiconductor package. The method comprises processing a semiconductor device, for example a semiconductor chip and processing a device carrier, for example a substrate. The semiconductor device comprises bump structures formed on a surface thereof. The substrate comprises bond pads formed on a surface thereof. Processing of the semiconductor chip results in heating of the semiconductor chip to a chip process temperature. The chip process temperature melts solder portions on the bump structures Processing of the substrate results in heating of the substrate to a substrate process temperature. The method comprises spatially aligning the semiconductor chip in relation to the substrate to correspondingly align the bump structures in relation to the bump pads. The semiconductor chip is then displaced towards the substrate for abutting the bump structures of the semiconductor chip with the bond pads of the substrate to thereby form bonds therebetween.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device has an active surface. The semiconductor device includes at least a connecting element and at least a bump. The connecting element is disposed on the activate surface and has a minimum dimension smaller than 100 microns. The bump is disposed on the connecting element and is electrically connected to the active surface by the connecting element. The bump includes a pillar part disposed on the connecting element and a top part disposed at the top of the pillar part. The pillar part has a first dimension and a second dimension both parallel to the active surface. The first dimension is longer than 1.2 times the second dimension. The top part is composed of solder and will melt under the determined temperature. The pillar part will not melt under a determined temperature.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device has an active surface. The semiconductor device includes at least a connecting element and at least a bump. The connecting element is disposed on the activate surface and has a minimum dimension smaller than 100 microns. The bump is disposed on the connecting element and is electrically connected to the active surface by the connecting element. The bump includes a pillar part disposed on the connecting element and a top part disposed on the top of the pillar part. The pillar part has a first dimension and a second dimension both parallel to the active surface. The first dimension is more than 1.2 times the second dimension. The top part is composed of solder and will melt under a pre-determined temperature. The pillar part will not melt under the pre-determined temperature.

Abstract: A package structure including a first semiconductor element, a second semiconductor element, a semiconductor interposer and a substrate is provided. The first semiconductor element includes multiple first conductive bumps. The second semiconductor element includes multiple second conductive bumps. The semiconductor interposer includes a connection motherboard, at least one signal wire and at least one signal conductive column. The signal wire is disposed on the connection motherboard. The two ends of the signal wire are electrically connected to one of the first conductive bumps and one of the second conductive bumps respectively. The signal conductive column is electrically connected to the signal wire. The substrate is electrically connected to the signal conductive column. The first and the second semiconductor elements have the same circuit structure. The substrate of the package structure can simultaneously form a signal communication path with the first and the second semiconductor element respectively.

Abstract: The invention discloses a package structure including a semiconductor device, a first protection layer, a second protection layer and at least one conductive connector. The semiconductor device has at least one pad. The first protection layer is disposed on the semiconductor device and exposes the pad. The second protection layer, disposed on the first protection layer, has at least one first opening and at least one second opening. The first opening exposes a partial surface of the pad. The second opening exposes a partial surface of the first protection layer. The conductive connector, opposite to the pad, is disposed on the second protection layer and coupled to the pad through the first openings.

Abstract: Embodiments relate to a method for fabricating nano-wires in nano-devices, and more particularly to nano-device fabrication using end-of-range (EOR) defects. In one embodiment, a substrate with a surface crystalline layer over the substrate is provided and EOR defects are created in the surface crystalline layer. One or more fins with EOR defects embedded within is formed and oxidized to form one or more fully oxidized nano-wires with nano-crystals within the core of the nano-wire.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device has an active surface. The semiconductor device includes at least a connecting element and at least a bump. The connecting element is disposed on the activate surface and has a minimum dimension smaller than 100 microns. The bump is disposed on the connecting element and is electrically connected to the active surface by the connecting element. The bump includes a pillar part disposed on the connecting element and a top part disposed at the top of the pillar part. The pillar part has a first dimension and a second dimension both parallel to the active surface. The first dimension is longer than 1.2 times the second dimension. The top part is composed of solder and will melt under the determined temperature. The pillar part will not melt under a determined temperature.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device has an active surface. The semiconductor device includes at least a connecting element and at least a bump. The connecting element is disposed on the activate surface and has a minimum dimension smaller than 100 microns. The bump is disposed on the connecting element and is electrically connected to the active surface by the connecting element. The bump includes a pillar part disposed on the connecting element and a top part disposed on the top of the pillar part. The pillar part has a first dimension and a second dimension both parallel to the active surface. The first dimension is longer than 1.2 times the second dimension. The top part is composed of solder and will melt under a pre-determined temperature. The pillar part will not melt under the pre-determined temperature.

Abstract: A package structure including a first semiconductor element, a second semiconductor element, a semiconductor interposer and a substrate is provided. The first semiconductor element includes multiple first conductive bumps. The second semiconductor element includes multiple second conductive bumps. The semiconductor interposer includes a connection motherboard, at least one signal wire and at least one signal conductive column. The signal wire is disposed on the connection motherboard. The two ends of the signal wire are electrically connected to one of the first conductive bumps and one of the second conductive bumps respectively. The signal conductive column is electrically connected to the signal wire. The substrate is electrically connected to the signal conductive column. The first and the second semiconductor elements have the same circuit structure. The substrate of the package structure can simultaneously form a signal communication path with the first and the second semiconductor element respectively.

Abstract: A method for fabricating a semiconductor device is presented. The method includes providing a substrate and forming a gate stack over the substrate. A first laser processing to form vacancy rich regions within the substrate on opposing sides of the gate stack is performed. The vacancy rich regions have a first depth from a surface of the substrate. A first implant causing end of range defect regions to be formed on opposing sides of the gate stack at a second depth from the surface of the substrate is also carried out, wherein the first depth is proximate to the second depth.

Abstract: Embodiments relate to a method for fabricating nano-wires in nano-devices, and more particularly to nano-device fabrication using end-of-range (EOR) defects. In one embodiment, a substrate with a surface crystalline layer over the substrate is provided and EOR defects are created in the surface crystalline layer. One or more fins with EOR defects embedded within is formed and oxidized to form one or more fully oxidized nano-wires with nano-crystals within the core of the nano-wire.

Abstract: A method for fabricating a flip-chip semiconductor package. The method comprises processing a semiconductor device, for example a semiconductor chip and processing a device carrier, for example a substrate. The semiconductor device comprises bump structures formed on a surface thereof. The substrate comprises bond pads formed on a surface thereof. Processing of the semiconductor chip results in heating of the semiconductor chip to a chip process temperature. The chip process temperature melts solder portions on the bump structures Processing of the substrate results in heating of the substrate to a substrate process temperature. The method comprises spatially aligning the semiconductor chip in relation to the substrate to correspondingly align the bump structures in relation to the bump pads. The semiconductor chip is then displaced towards the substrate for abutting the bump structures of the semiconductor chip with the bond pads of the substrate to thereby form bonds therebetween.

Abstract: A process for forming a strained channel region for a MOSFET device via formation of adjacent silicon-germanium source/drain regions, has been developed. The process features either blanket deposition of a silicon-germanium layer, or selective growth of a silicon-germanium layer on exposed portions of a source/drain extension region. A laser anneal procedure results in formation of a silicon-germanium source/drain region via consumption of a bottom portion of the silicon-germanium layer and a top portion of the underlying source/drain region. Optimization of the formation of the silicon-germanium source/drain region via laser annealing can be achieved via a pre-amorphization implantation (PAI) procedure applied to exposed portions of the source/drain region prior to deposition of the silicon-germanium layer. Un-reacted top portions of the silicon-germanium layer are selectively removed after the laser anneal procedure.

Abstract: A method for forming a shallow junction region in a crystalline semiconductor substrate and method for fabricating a semiconductor device having the shallow junction region includes a defect engineering step in which first ions are introduced into a first region of the substrate and vacancies are generated in the first region. During the generation of substrate vacancies, the first region remains substantially crystalline. Interstitial species are generated in a second region and second ions are introduced into the second region to capture the interstitial species. Laser annealing is used to activate dopant species in the first region and repair implantation damage in the second region. The defect engineering process creates a vacancy-rich surface region in which source and drain extension regions having high dopant activation and low sheet resistance are created in an MOS device.

Abstract: A method for forming a shallow junction region in a crystalline semiconductor substrate and method for fabricating a semiconductor device having the shallow junction region includes a defect engineering step in which first ions are introduced into a first region of the substrate and vacancies are generated in the first region. During the generation of substrate vacancies, the first region remains substantially crystalline. Interstitial species are generated in a second region and second ions are introduced into the second region to capture the interstitial species. Laser annealing is used to activate dopant species in the first region and repair implantation damage in the second region. The defect engineering process creates a vacancy-rich surface region in which source and drain extension regions having high dopant activation and low sheet resistance are created in an MOS device.