Abstract: A device is disclosed. The device includes a carrier substrate having first and second major surfaces. The first surface includes a die region and contact pads and the second surface includes package contacts. The carrier substrate includes a patterned lead frame which defines a line level with conductive traces and a via level with via contacts. The patterned lead frame provides interconnections between the contact pads and package contacts. The carrier substrate further includes a dielectric layer isolating the conductive traces and via contacts. The device includes a die mounted on the die region of the first surface.

Abstract: A device is disclosed. The device includes a carrier substrate having first and second major surfaces. The first surface includes a die region and contact pads and the second surface includes package contacts. The carrier substrate includes a patterned lead frame which defines a line level with conductive traces and a via level with via contacts. The patterned lead frame provides interconnections between the contact pads and package contacts. The carrier substrate further includes a dielectric layer isolating the conductive traces and via contacts. The device includes a die mounted on the die region of the first surface.

Abstract: A device is disclosed. The device includes a carrier substrate having first and second major surfaces. The first surface includes a die region and contact pads and the second surface includes package contacts. The carrier substrate includes a patterned lead frame which defines a line level with conductive traces and a via level with via contacts. The patterned lead frame provides interconnections between the contact pads and package contacts. The carrier substrate further includes a dielectric layer isolating the conductive traces and via contacts. The device includes a die mounted on the die region of the first surface.

Abstract: A device is disclosed. The device includes a carrier substrate having first and second major surfaces. The first surface includes a die region and contact pads and the second surface includes package contacts. The carrier substrate includes a patterned lead frame which defines a line level with conductive traces and a via level with via contacts. The patterned lead frame provides interconnections between the contact pads and package contacts. The carrier substrate further includes a dielectric layer isolating the conductive traces and via contacts. The device includes a die mounted on the die region of the first surface.

Abstract: A device is disclosed. The device includes a carrier substrate having first and second major surfaces. The first surface includes a die region and contact pads and the second surface includes package contacts. The carrier substrate includes a patterned lead frame which defines a line level with conductive traces and a via level with via contacts. The patterned lead frame provides interconnections between the contact pads and package contacts. The carrier substrate further includes a dielectric layer isolating the conductive traces and via contacts. The device includes a die mounted on the die region of the first surface.

Abstract: A device is disclosed. The device includes a carrier substrate having first and second major surfaces. The first surface includes a die region and contact pads and the second surface includes package contacts. The carrier substrate includes a patterned lead frame which defines a line level with conductive traces and a via level with via contacts. The patterned lead frame provides interconnections between the contact pads and package contacts. The carrier substrate further includes a dielectric layer isolating the conductive traces and via contacts. The device includes a die mounted on the die region of the first surface.

Abstract: A device is disclosed. The device includes a carrier substrate having first and second major surfaces. The first surface includes a die region and contact pads and the second surface includes package contacts. The carrier substrate includes a patterned lead frame which defines a line level with conductive traces and a via level with via contacts. The patterned lead frame provides interconnections between the contact pads and package contacts. The carrier substrate further includes a dielectric layer isolating the conductive traces and via contacts. The device includes a die mounted on the die region of the first surface.

Abstract: A method of mounting a semiconductor die on a substrate with a solder mask on a first surface includes placing a die on the solder mask, and mounting the die to the substrate by applying pressure and heat. The applied pressure ranges from a bond force of approximately 5 to 10 kgf, the heat has a temperature range from approximately 150 to 200° C. and the pressure is applied for a range of approximately 1 to 10 seconds.

Abstract: A semiconductor package and a method for constructing the package are disclosed. The package includes a substrate and a die attached thereto. A first contact region is disposed on the substrate and a second contact region is disposed on the die. The first contact region, for example, comprises copper coated with an OSP material. A copper wire bond electrically couples the first and second contact regions. Wire bonding includes forming a ball bump on the first contact region having a flat top surface. Providing the flat top surface is achieved with a smoothing process. A ball bond is formed on the second contact region, followed by stitching the wire onto the flat top surface of the ball bump on the first contact region.

Abstract: A method of mounting a semiconductor die on a substrate with a solder mask on a first surface includes placing a die on the solder mask, and mounting the die to the substrate by applying pressure and heat. The applied pressure ranges from a bond force of approximately 5 to 10 Kg, the heat has a temperature range from approximately 150 to 200° C. and the pressure is applied for a range of approximately 1 to 10 seconds.

Abstract: A device is disclosed. The device includes a carrier substrate having first and second major surfaces. The first surface includes a die region and contact pads and the second surface includes package contacts. The carrier substrate includes a patterned lead frame which defines a line level with conductive traces and a via level with via contacts. The patterned lead frame provides interconnections between the contact pads and package contacts. The carrier substrate further includes a dielectric layer isolating the conductive traces and via contacts. The device includes a die mounted on the die region of the first surface.

Abstract: A method of forming a device is disclosed. The method includes providing a printed circuit board substrate having a die attach region on a first surface of the substrate. The method also includes attaching a die to a die attach region. The die is electrically coupled to first land pads disposed on the first surface at the periphery of the die attach region. A cap is formed in a target area by a top gate process to produce a cap with an even surface. The cap covers the die and leaves at least the first land pads exposed.

Abstract: A semiconductor package and a method for constructing the package are disclosed. The package includes a substrate and a die attached thereto. A first contact region is disposed on the substrate and a second contact region is disposed on the die. The first contact region, for example, comprises copper coated with an OSP material. A copper wire bond electrically couples the first and second contact regions. Wire bonding includes forming a ball bump on the first contact region having a flat top surface. Providing the flat top surface is achieved with a smoothing process. A ball bond is formed on the second contact region, followed by stitching the wire onto the flat top surface of the ball bump on the first contact region.

Abstract: A method of mounting a semiconductor die on a substrate with a solder mask on a first surface includes placing a die on the solder mask, and mounting the die to the substrate by applying pressure and heat. The applied pressure ranges from a bond force of approximately 5 to 10 Kg, the heat has a temperature range from approximately 150 to 200° C. and the pressure is applied for a range of approximately 1 to 10 seconds.

Abstract: A plasma clean tool that includes a cleaning chamber for cleaning an article by plasma cleaning and a charge shield for surrounding an article to be cleaned is presented. The charge shield prevents charged components of plasma from passing therethrough to charge the article during plasma cleaning of the article.

Abstract: Provided is a semiconductor package, and a method for constructing the same, including a first substrate, a first semiconductor chip attached to the first substrate, and a first copper wire. At least one of the first substrate and the first semiconductor chip has an Organic Solderability Preservative (OSP) material coated on at least a portion of one surface, and the first copper wire is wire bonded through the OSP material to the first substrate and the first semiconductor chip.

Abstract: The invention is a method for attaching an electronic component (40) having Ball Grid Array contacts (36) to a circuit board contact array (31) to prevent the solder balls (36) of the Ball Grid Array from fracturing and distorting during solder reflow when the Ball grid Array contact (36) is attached to a contact (31) on a printed circuit board (30) that has a via (32) extending at least partially though the printed circuit board (30). A solder form (35) is placed over each via (32) in each contact (31) of the contact array. The electronic component (40) that has BGA contacts (36) is placed over the contact array (31) such that each ball (36) of the ball grid array of the electronic component resides on a solder form (35). The component (40) and circuit board (30) is subjected to a solder reflow process to seal the component (40) to the circuit board (30). The solder form (35) at least partially fills the via (32) preventing the BGA contact (36) from collapsing into the via (32).

Abstract: An integrated circuit package (30, 32) for vertical attachment as part of a high density module (200) comprising a carrier (70) having an opening (86), routing strips (82), conduits (84) and side surface terminals (100), the side surface terminals (100) disposed on a side surface (92), which side surface is common to the carrier (70) and the integrated circuit package 30, 32. An adhesive layer (60), which attaches a silicon chip (50) to a carrier (70), wire bonding (80) electrically connecting the silicon chip (50) to the routing strips (82) and potting material (90) filling the opening (86), are also disclosed.

Abstract: A method and apparatus for producing an integrated circuit package (30) comprising a substrate (70) having an opening (86) and first and second surfaces (92, 94), a plurality of routing strips (82) being integral with the substrate (70) and extending into the opening (86), a plurality of pads (100) disposed on the first and second surfaces (92, 94) are electrically connected with at least one of the routing strips (82), wire bonding (80) electrically connecting at least one bonding pad (120) to at least one of the routing strips (82) and a silicon chip (50) attached to the printed circuit board (70) by an adhesive material (60) that provide a seal between silicon chip (50) and printed circuit board (70) is disclosed.

Abstract: A method and apparatus for producing an integrated circuit package (30) comprising a substrate (70) having an opening (86) and first and second surfaces (92, 94), a plurality of routing strips (82) being integral with the substrate (70) and extending into the opening (86), a plurality of pads (100) disposed on the first and second surfaces (92, 94) are electrically connected with at least one of the routing strips (82), wire bonding (80) electrically connecting at least one bonding pad (120) to at least one of the routing strips (82) and a silicon chip (50) attached to the printed circuit board (70) by an adhesive material (60) that provide a seal between silicon chip (50) and printed circuit board (70) is disclosed.