Patents by Inventor Kian Teng Eng

Kian Teng Eng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020001882
    Abstract: A method and apparatus for producing an integrated circuit package (30) comprising a substrate (70) having an opening (86) and first and second surfaces (92, 94), a plurality of routing strips (82) being integral with the substrate (70) and extending into the opening (86), a plurality of pads (100) disposed on the first and second surfaces (92, 94) are electrically connected with at least one of the routing strips (82), wire bonding (80) electrically connecting at least one bonding pad (120) to at least one of the routing strips (82) and a silicon chip (50) attached to the printed circuit board (70) by an adhesive material (60) that provide a seal between silicon chip (50) and printed circuit board (70) is disclosed.
    Type: Application
    Filed: July 6, 2001
    Publication date: January 3, 2002
    Inventors: Kian Teng Eng, Min Yu Chan, Jing Sua Goh, Siu Waf Low, Boon Pew Chan, Tuck Fook Toh, Chee Kiang Yew, Pak Hong Yee
  • Patent number: 6320126
    Abstract: An integrated circuit package (30, 32) for vertical attachment as part of a high density module (200) having a carrier (70) having an opening (86), routing strips (82), conduits (84) and side surface terminals (100), the side surface terminals (100) disposed on a side surface (92), which side surface is common to the carrier (70) and the integrated circuit package 30, 32. An adhesive layer (60), which attaches a silicon chip (50) to a carrier (70), wire bonding (80) electrically connecting the silicon chip (50) to the routing strips (82) and potting material (90) filling the opening (86), are also disclosed.
    Type: Grant
    Filed: July 14, 1998
    Date of Patent: November 20, 2001
    Assignee: Texas Instruments Incorporated
    Inventors: Kian Teng Eng, Lee Teck Yeow
  • Patent number: 6177723
    Abstract: An integrated circuit package having a top opening and a cavity, with a chip adhered in the cavity. The top opening has routing strips electrically connecting the top opening with the outer surface. The routing strips are electronically connected to bonding pads located in a central area of the chip. Following assembly of the components, the top opening and the cavity are encapsulated in a molding process. A method is provided for forming a substantially flat integrated circuit package.
    Type: Grant
    Filed: December 17, 1997
    Date of Patent: January 23, 2001
    Assignee: Texas Instruments Incorporated
    Inventors: Kian Teng Eng, Min Yu Chan, Jing Sua Goh, Boon Pew Chan
  • Patent number: 6087203
    Abstract: A method and apparatus for producing an integrated circuit package (30) comprising a substrate (70) having an opening (86) and first and second surfaces (92, 94), a plurality of routing strips (82) being integral with the substrate (70) and extending into the opening (86), a plurality of pads (100) disposed on the first and second surfaces (92, 94) are electrically connected with at least one of the routing strips (82), wire bonding (80) electrically connecting at least one bonding pad (120) to at least one of the routing strips (82) and a silicon chip (50) attached to the printed circuit board (70) by an adhesive material (60) that provide a seal between silicon chip (50) and printed circuit board (70) is disclosed.
    Type: Grant
    Filed: December 19, 1997
    Date of Patent: July 11, 2000
    Assignee: Texas Instruments Incorporated
    Inventors: Kian Teng Eng, Min Yu Chan, Jing Sua Goh, Siu Waf Low, Boon Pew Chan, Tuck Fook Toh, Chee Kiang Yew, Pak Hong Yee
  • Patent number: 6084306
    Abstract: An integrated circuit package (30) having first and second layers (76, 78), a plurality of routing pads (82) being integral with the first layer (76), a plurality of upper and lower conduits (18, 118), respectively, disposed on the upper and lower surfaces (92, 94) of the first layer (76), at least one of the upper conduits (18) electrically connected to at least one of the lower conduits (118), a plurality of pads (100) disposed on the second layer (78), vias (84) that electrically connect the pads (100) to the lower conduits (118) and a chip (50) adhered to the second layer (78) having bonding pads (120) at least one of which is electrically connected to at least one of the routing pads (82), is disclosed.
    Type: Grant
    Filed: May 29, 1998
    Date of Patent: July 4, 2000
    Assignee: Texas Instruments Incorporated
    Inventors: Chee Kiang Yew, Kian Teng Eng, Ji Cheng Yang
  • Patent number: 5998860
    Abstract: A double sided single inline memory module (20) comprising a substrate (70) having a plurality of openings (86) and first and second surfaces (92, 94), a plurality of pads (82) being integral with the substrate (70) and extending into the opening (86), a plurality of chips (50) adhered to the substrate (70) having bonding pads (120), wire bonding (80) electrically connecting at least one of the bonding pads (120) to at least one of the pads (82) and potting material (90) encapsulating the wire bonding (80) and filling the opening (86) is disclosed.
    Type: Grant
    Filed: December 19, 1997
    Date of Patent: December 7, 1999
    Assignee: Texas Instruments Incorporated
    Inventors: Boon Pew Chan, Kian Teng Eng
  • Patent number: 5956233
    Abstract: A high density single inline memory module (140) comprising a printed circuit board (132) and at least one integrated circuit module (130) attached to the first side (134) of the printed circuit board (132), wherein the integrated circuit modules (130) each including first and second integrated circuit packages (30) stackably and electrically connected together is disclosed.
    Type: Grant
    Filed: December 19, 1997
    Date of Patent: September 21, 1999
    Assignee: Texas Instruments Incorporated
    Inventors: Chee Kiang Yew, Kian Teng Eng, Sian Yong Khoo, Bok Leng Ser
  • Patent number: 5952611
    Abstract: An integrated circuit package (30) including a substrate (70) having an opening (86) and first and second surfaces(92, 94), a plurality of pads (100) disposed on the first and second surfaces (92, 94) having disposed thereon solder balls (150) electrically connected by a via (84) that provides the end-user with flexibility in the location of a power supply Pin (96) is disclosed.
    Type: Grant
    Filed: December 19, 1997
    Date of Patent: September 14, 1999
    Assignee: Texas Instruments Incorporated
    Inventors: Kian Teng Eng, Min Yu Chan, Jing Sua Goh, Siu Waf Low
  • Patent number: 5798564
    Abstract: The invention is to a double side semiconductor module (10) and an array (40) made up of a plurality of stacked modules (10). Each module (10) includes a plurality of substrates (11-15). A first substrate (13) has first and second sides, with one semiconductor device (16,25) having bond pads thereon (17,26), mounted on each of said first and second sides. At least one additional substrate (12,14) having a central opening (12b,14b), is placed on each of said first and second sides with the semiconductor device (16,25) mounted in the central opening (12b,14b). A plurality of solder pins (11a-15a), associated with each of said substrates (11-15) are connected to contact pads (17,26) on the semiconductor devices (16,25), and extend from and to openings in said substrates (11-15).
    Type: Grant
    Filed: December 20, 1996
    Date of Patent: August 25, 1998
    Assignee: Texas Instruments Incorporated
    Inventors: Kian Teng Eng, Jing Sua Goh