Patents by Inventor Kikuo Aida

Kikuo Aida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10998437
    Abstract: A semiconductor device according to an embodiment includes a semiconductor substrate having a first plane and a second plane, a semiconductor element provided in the semiconductor substrate, the semiconductor element including a gate insulating film provided in the first plane, a first electrode provided on the first plane, a second electrode provided on the first electrode, the second electrode including a first metal material, the second electrode having a film thickness of (65 [g·?m·cm?3])/(density of the first metal material [g·cm?3]) or more, a first solder portion provided on the second electrode, a third electrode provided on the first solder portion, a fourth electrode provided on the first plane, a fifth electrode provided on the fourth electrode, the fifth electrode including a second metal material, the fifth electrode having a film thickness of (65 [g·?m·cm?3])/(density of the second metal material [g·cm?3]) or more, a second solder portion provided on the fifth electrode, and a sixth electrode pr
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: May 4, 2021
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Tatsuya Ohguro, Tatsuya Nishiwaki, Hideharu Kojima, Yoshiharu Takada, Kikuo Aida, Kentaro Ichinoseki, Kohei Oasa, Shingo Sato
  • Publication number: 20200295180
    Abstract: According to one embodiment, a semiconductor device includes: a semiconductor layer including a first plane extending along a plane including a first axis and a second axis; a first electrode extending along the first axis; a second electrode extending along the second axis; and a third electrode above the first plane. The third electrode is electrically coupled to the first electrode and the second electrode, and includes a first portion, a second portion and a third portion. The first portion crosses the first electrode. The second portion crosses the second electrode. The third portion crosses the second electrode and is separate at a first end from the second portion.
    Type: Application
    Filed: September 3, 2019
    Publication date: September 17, 2020
    Applicants: KABUSHIKI KAISHA TOSHIBA, Toshiba Electronic Devices & Storage Corporation
    Inventors: Kentaro ICHINOSEKI, Tatsuya NISHIWAKI, Kikuo AIDA, Kohei OASA
  • Patent number: 10763352
    Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type having first and second surfaces and an impurity concentration distribution in a first direction from the second surface to the first surface, a first semiconductor region of a second conductivity between the semiconductor layer and the first surface, a second semiconductor region of a first conductivity type between the first semiconductor region and the first surface side, a first trench extending from the first surface into the semiconductor layer, a first electrode located in the first trench over a first insulating film and spaced from the first semiconductor region by a first insulating film, a second electrode located in the first trench over a second insulating film, a second trench extending from the first surface into the semiconductor layer and surrounding the first trench, and a third electrode located in the second trench over a third insulating film.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: September 1, 2020
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Hiroshi Matsuba, Hung Hung, Tatsuya Nishiwaki, Kohei Oasa, Kikuo Aida
  • Patent number: 10707312
    Abstract: According to one embodiment, there is provided a semiconductor device including a semiconductor substrate, a plurality of first columnar bodies having a peripheral edge, each of the columnar bodies spaced from one another on the semiconductor substrate, each including a first conductive layer extending from an upper end thereof in the depth direction of the semiconductor substrate, a base layer deposited about an outer peripheral surface of an upper end of the plurality of first columnar bodies, a gate adjacent to the base layer with a gate insulating film therebetween, a source layer connected to the base layer, and a second columnar body, including a second conductive layer, surrounding an outer peripheral edge of the plurality of first columnar bodies and extending in the depth direction of the semiconductor substrate.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: July 7, 2020
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Hiroshi Matsuba, Hung Hung, Tatsuya Nishiwaki, Kikuo Aida, Kohei Oasa
  • Publication number: 20200152785
    Abstract: A semiconductor device according to an embodiment includes a semiconductor substrate having a first plane and a second plane, a semiconductor element provided in the semiconductor substrate, the semiconductor element including a gate insulating film provided in the first plane, a first electrode provided on the first plane, a second electrode provided on the first electrode, the second electrode including a first metal material, the second electrode having a film thickness of (65 [g·?m·cm?3])/(density of the first metal material [g·cm?3]) or more, a first solder portion provided on the second electrode, a third electrode provided on the first solder portion, a fourth electrode provided on the first plane, a fifth electrode provided on the fourth electrode, the fifth electrode including a second metal material, the fifth electrode having a film thickness of (65 [g·m·cm?3])/(density of the second metal material [g·cm?3]) or more, a second solder portion provided on the fifth electrode, and a sixth electrode pro
    Type: Application
    Filed: August 5, 2019
    Publication date: May 14, 2020
    Applicants: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Tatsuya OHGURO, Tatsuya NISHIWAKI, Hideharu KOJIMA, Yoshiharu TAKADA, Kikuo AIDA, Kentaro ICHINOSEKI, Kohei OASA, Shingo SATO
  • Patent number: 10651276
    Abstract: A semiconductor device has a cell which includes a first semiconductor region of a first conductive type, a base region of a second conductive type on the first semiconductor region, a source region of the first conductive type on the base region, a gate electrode penetrating through the base region in a first direction to reach the first semiconductor region and extending in a second direction, and a gate insulting film between the gate electrode and the first semiconductor region, between the gate electrode and the base region, and between the gate electrode and the source region. The cell has a region having a first threshold voltage and a region having a second threshold voltage higher than the first threshold voltage.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: May 12, 2020
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Tatsuya Nishiwaki, Kohei Oasa, Hiroshi Matsuba, Hung Hung, Kikuo Aida, Kentaro Ichinoseki
  • Patent number: 10593793
    Abstract: A semiconductor device according to an embodiment includes: a first semiconductor region of a first conductive type; a base region of a second conductive type; gate electrodes penetrating through the base region to reach the first semiconductor region; gate insulating films around the plurality of gate electrodes; a first region having a source region of the first conductive type, among a plurality of regions between the plurality of gate insulating films; a second region not having the source region among the plurality of regions, the second region being located in a terminal region of the first region; a first contact of a first width in the first region and electrically connecting the base region and a source electrode; and a second contact of a second width larger than the first width, the second contact being in the second region and electrically connecting the base region and the source electrode.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: March 17, 2020
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Tatsuya Nishiwaki, Kohei Oasa, Hiroshi Matsuba, Kikuo Aida, Hung Hung
  • Publication number: 20190296116
    Abstract: According to one embodiment, there is provided a semiconductor device including a semiconductor substrate, a plurality of first columnar bodies having a peripheral edge, each of the columnar bodies spaced from one another on the semiconductor substrate, each including a first conductive layer extending from an upper end thereof in the depth direction of the semiconductor substrate, a base layer deposited about an outer peripheral surface of an upper end of the plurality of first columnar bodies, a gate adjacent to the base layer with a gate insulating film therebetween, a source layer connected to the base layer, and a second columnar body, including a second conductive layer, surrounding an outer peripheral edge of the plurality of first columnar bodies and extending in the depth direction of the semiconductor substrate.
    Type: Application
    Filed: August 31, 2018
    Publication date: September 26, 2019
    Inventors: Hiroshi MATSUBA, Hung HUNG, Tatsuya NISHIWAKI, Kikuo AIDA, Kohei OASA
  • Publication number: 20190288103
    Abstract: A semiconductor device according to an embodiment includes: a first semiconductor region of a first conductive type; a base region of a second conductive type; gate electrodes penetrating through the base region to reach the first semiconductor region; gate insulating films around the plurality of gate electrodes; a first region having a source region of the first conductive type, among a plurality of regions between the plurality of gate insulating films; a second region not having the source region among the plurality of regions, the second region being located in a terminal region of the first region; a first contact of a first width in the first region and electrically connecting the base region and a source electrode; and a second contact of a second width larger than the first width, the second contact being in the second region and electrically connecting the base region and the source electrode.
    Type: Application
    Filed: September 10, 2018
    Publication date: September 19, 2019
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Tatsuya NISHIWAKI, Kohei OASA, Hiroshi MATSUBA, Kikuo AIDA, Hung HUNG
  • Publication number: 20190288071
    Abstract: A semiconductor device has a cell which includes a first semiconductor region of a first conductive type, a base region of a second conductive type on the first semiconductor region, a source region of the first conductive type on the base region, a gate electrode penetrating through the base region in a first direction to reach the first semiconductor region and extending in a second direction, and a gate insulting film between the gate electrode and the first semiconductor region, between the gate electrode and the base region, and between the gate electrode and the source region. The cell has a region having a first threshold voltage and a region having a second threshold voltage higher than the first threshold voltage.
    Type: Application
    Filed: September 12, 2018
    Publication date: September 19, 2019
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Tatsuya NISHIWAKI, Kohei OASA, Hiroshi MATSUBA, Hung HUNG, Kikuo AIDA, Kentaro ICHINOSEKI
  • Publication number: 20190259871
    Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type having first and second surfaces and an impurity concentration distribution in a first direction from the second surface to the first surface, a first semiconductor region of a second conductivity between the semiconductor layer and the first surface, a second semiconductor region of a first conductivity type between the first semiconductor region and the first surface side, a first trench extending from the first surface into the semiconductor layer, a first electrode located in the first trench over a first insulating film and spaced from the first semiconductor region by a first insulating film, a second electrode located in the first trench over a second insulating film, a second trench extending from the first surface into the semiconductor layer and surrounding the first trench, and a third electrode located in the second trench over a third insulating film.
    Type: Application
    Filed: August 31, 2018
    Publication date: August 22, 2019
    Inventors: Hiroshi MATSUBA, Hung HUNG, Tatsuya NISHIWAKI, Kohei OASA, Kikuo AIDA
  • Publication number: 20190081173
    Abstract: A semiconductor device which includes a semiconductor layer, a first electrode, a second electrode, first trenches, a second trench surrounding the first trenches, a gate electrode and a first field plate electrode in the first trenches, a first insulating layer including a first portion p having a first film thickness, a second portion having a second film thickness thicker than the first film thickness, and a third portion having a third film thickness thicker than the second film thickness, a second field plate electrode in the second trench, a second insulating layer in the second trench. The semiconductor layer includes a first semiconductor region having a first conductivity type, a second semiconductor region having a second conductivity type, and a third semiconductor region having the second conductivity type.
    Type: Application
    Filed: February 23, 2018
    Publication date: March 14, 2019
    Inventors: Tatsuya NISHIWAKI, Kentaro ICHINOSEKI, Kikuo AIDA, Kohei OASA, Hung HUNG, Hiroshi MATSUBA
  • Patent number: 4984526
    Abstract: A thread chain guiding device provides a needle-thread-guide plate which extends underneath a throat plate by energizing a solenoid as needed. Thus, the needle-thread-guide plate pushes the needle threads twined around a lower looper outwardly away such that the thread chain is prevented from hanging on an inner chain-off finger when it is rotated counter clockwise. The needle-thread-guide plate is retracted during a normal stitching process by de-energizing the solenoid.
    Type: Grant
    Filed: May 23, 1989
    Date of Patent: January 15, 1991
    Assignee: Juki Corporation
    Inventors: Hiroshi Ide, Kikuo Aida, Shingo Iwae
  • Patent number: 4777892
    Abstract: A thread chain is prevented from hanging at an inner chain-off finger when it is turned back or rotated to the operator's side for holding and cutting. A needle thread, positioned at the front side of a lower looper, is guided by a needle thread restricting device, and a needle thread positioned on the back side of a lower looper is prevented from being hung on an inner chain-off finger by a thread chain guiding device provided at a throat plate so that enfolding back and tacking of the thread chain into the fabric material is performed well.
    Type: Grant
    Filed: June 25, 1986
    Date of Patent: October 18, 1988
    Assignee: Tokyo Juki Industrial Co., Ltd.
    Inventors: Kikuo Aida, Shingo Iwae
  • Patent number: 4774900
    Abstract: In a two-needle overedge sewing machine, a thread chain guide recess is formed for positioning the thread chain at a given position on the throat plate so that the thread chain is spaced apart from the outer needle descending point. The thread chain guide recess may be made at a tip portion of an outer finger of the throat plate or at a tip portion of an outer finger of a presser foot. Furthermore, the thread chain guide recess may be formed by the combination of the outer finger of the throat plate and the outer finger of the presser foot. In an improved embodiment, a thread chain guide groove is formed in an upper surface of the outer finger of the throat plate so that the thread chain is substantially fully received therein.
    Type: Grant
    Filed: June 24, 1986
    Date of Patent: October 4, 1988
    Assignee: Tokyo Juki Industrial Co., Ltd.
    Inventors: Kikuo Aida, Shingo Iwae
  • Patent number: 4726308
    Abstract: A thread tension control device for overedging sewing machines wherein each needle thread tension controller and each looper thread tension controller provide two springs designed to clamp two tension discs wherethrough a thread is passed. A slide plate, by its horizontal sliding motion, either causes the two springs to be active or causes one of the two springs to be released thereby obtaining either strong or weak thread tension. A workpiece end detector defines either an overedging process or thread chain forming process and sends a signal to actuate the horizontal sliding motion of the slide plate. Thus, the proper thread tensioning for each needle thread and each looper thread for either an overedging process or a thread chain forming process may be automatically adjusted.
    Type: Grant
    Filed: October 17, 1986
    Date of Patent: February 23, 1988
    Assignee: Tokyo Juki Industrial Co., Ltd.
    Inventors: Kikuo Aida, Shingo Iwae
  • Patent number: 4285294
    Abstract: An upper layer feed mechanism in a sewing machine is disclosed herein. The upper layer feed mechanism comprises a first interlocking arm secured at one end to a horizontal feed shaft, an upper layer feed shaft rotatably supported on the machine frame of a sewing machine and having a second interlocking arm, a connector rod connecting between the first and second interlocking arms, an adjusting mechanism adjusting the connection between the second interlocking arm and connector rod, a support arm rotatably supported at one end on the machine frame, an upper layer feed arm rotatably supported at one end on the support arm and having an upper layer feed dog at the other end, a connection mechanism transmitting the rocking movement of the upper feed shaft to the support arm, a resilient means normally urging the upper layer feed dog downwardly and a means urging the upper layer feed dog upwardly against the resiliency of the resilient means.
    Type: Grant
    Filed: June 26, 1980
    Date of Patent: August 25, 1981
    Assignee: Tokyo Juki Kogyo Kabushiki Kaisha
    Inventor: Kikuo Aida