Semiconductor device
According to one embodiment, there is provided a semiconductor device including a semiconductor substrate, a plurality of first columnar bodies having a peripheral edge, each of the columnar bodies spaced from one another on the semiconductor substrate, each including a first conductive layer extending from an upper end thereof in the depth direction of the semiconductor substrate, a base layer deposited about an outer peripheral surface of an upper end of the plurality of first columnar bodies, a gate adjacent to the base layer with a gate insulating film therebetween, a source layer connected to the base layer, and a second columnar body, including a second conductive layer, surrounding an outer peripheral edge of the plurality of first columnar bodies and extending in the depth direction of the semiconductor substrate.
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This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2018-053358, filed Mar. 20, 2018, the entire contents of which are incorporated herein by reference.
FIELDEmbodiments described herein relate generally to a semiconductor device.
BACKGROUNDAs a structure for improving a cell breakdown voltage and on-resistance of a power MOSFET having a trench type field plate electrode structure, a structure in which a field plate electrode is embedded in a stripe shaped trench is known. In addition, in order to reduce the on-resistance, a power MOSFET having a column trench type field plate structure in which a field plate electrode is formed in a column shape to reduce an ineffective region where an on current does not flow, is known.
However, in the stripe trench type field plate structure, the distance between the field plate electrodes is constant, and in the column trench structure, the distance between the field plate electrodes tends to be non-uniform and there is a problem that the breakdown voltage of the device is lowered.
Embodiments provide a semiconductor device having improved breakdown voltage.
According to the embodiment, there is provided a semiconductor device including a semiconductor substrate, a plurality of first columnar bodies having a peripheral edge, each of the columnar bodies spaced from one another on the semiconductor substrate, each including a first conductive layer extending from an upper end thereof in the depth direction of the semiconductor substrate, a base layer positioned or deposited about an outer peripheral surface of an upper end of the plurality of first columnar bodies, a gate located adjacent to the base layer with a gate insulating film therebetween, a source layer connected to the base layer, and a second columnar body, including a second conductive layer, surrounding an outer peripheral edge of the plurality of first columnar bodies and extending in the depth direction of the semiconductor substrate.
Hereinafter, an embodiment of the present disclosure will be described with reference to the drawings. In the drawings attached to the present specification, for convenience of illustration and ease of understanding, the scales and the dimensional ratios of length and width are appropriately changed from those of actual devices and the sizes and ratios may be exaggerated.
Furthermore, as used in the present specification, it shall be interpreted that terms such as “parallel”, “orthogonal”, “same”, and the like, values of length, angle, and the like, which specify shapes and geometric conditions and their degrees are not bound by a strict meaning and their scope of interpretation includes a range thereof where one can expect the same functionality of the described device.
The semiconductor device 1 of
As shown in
As shown in
A termination trench 11 is formed so as to surround the outer peripheral edges of a plurality of FP trenches 4 in a first direction X and a second direction Y in the plane of the semiconductor device 1. The termination trench 11 has approximately the same width and depth as the FP trenches 4. Inside of the termination trench 11, an insulating film 12 and a termination electrode 13 are formed. The termination electrode 13 is electrically connected to the source layer 8. The termination trench 11 is formed in a shape following the outer shape of the plurality of FP trenches 4 arranged at the outer periphery. In the present specification, the insulating film 12 and the termination electrode 13 in the termination trench 11 are referred to as a second columnar body.
As shown in
In addition, as shown in
In addition, as shown in
The gate wiring layer 17 is in a location where the source wiring layer 15 is not disposed. This prevents a problem such as a short circuit between the gate wiring layer 17 and the source wiring layer 15.
In
In a case of
For example, in a case of
In the case of
Next, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
Thus, in the embodiment, since the respective FP trenches 4 are arranged in a zigzag manner with constant pitches between three adjacent FP trenches 4, it is possible to equalize the distances between adjacent field plate electrodes 6, to provide a uniform breakdown voltage thereof, and to improve the breakdown voltage of the device.
In addition, in the embodiment, since the termination trenches 11 are arranged so as to surround the plurality of FP trenches 4 two-dimensionally arranged in the plane and the shape of the termination trenches 11 is formed along the outer peripheral edge of the plurality of FP trenches 4, it is possible to uniformly form the distance between the termination electrode 13 in the termination trench 11 and the FP trench 4 in a cell portion and to also improve the breakdown voltage of the device.
Furthermore, by forming the cross-sectional shape of the FP trench 4 as a regular hexagonal shape, the depletion layers 18 spreading in the vicinity of the FP trench 4 are in surface contact with each other and the drift layer can be uniformly depleted such that the electric field distribution becomes uniform and the breakdown voltage of the device can be improved.
In addition, by forming the termination trench 11 in accordance with an outer shape of the FP trench 4, it is possible to further provide a uniform distance between the termination trench 11 and the adjacent field plate electrodes 6 and the breakdown voltage of the device can be further improved.
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.
Claims
1. A semiconductor device, comprising:
- a semiconductor substrate;
- a plurality of first columnar bodies having a peripheral edge, each of the columnar bodies spaced from one another on the semiconductor substrate, each including a first conductive layer extending from an upper end thereof in the depth direction of the semiconductor substrate;
- a base layer deposited about an outer peripheral surface of an upper end of the plurality of first columnar bodies;
- a gate layer adjacent to the base layer with a gate insulating film therebetween;
- a source layer connected to the base layer;
- a second columnar body, including a second conductive layer, surrounding an outer peripheral edge of the plurality of first columnar bodies and extending in the depth direction of the semiconductor substrate;
- a source wiring layer above the first conductive layer in each of the plurality of first columnar bodies and above at least a part of the second conductive layer, and electrically connected to the first conductive layer in each of the plurality of first columnar bodies and to the second conductive layer in the second columnar body; and
- a gate lead-out layer that extends from a first region surrounded by the second columnar body over the second columnar body to a second region outside the first region and is electrically connected to the gate layer, the gate lead-out layer being electrically separated from the first conductive layer in each of the first columnar bodies and the second conductive layer in the second columnar body.
2. The semiconductor device according to claim 1, wherein three adjacent first columnar bodies of the plurality of first columnar bodies are equally spaced from one another.
3. The semiconductor device of claim 1, wherein the source layer is electrically connected to the plurality of first conductive layers.
4. The semiconductor device according to claim 1, further comprising:
- a first contact extending between and electrically connecting the source wiring layer and the first conductive layer in each of the plurality of first columnar bodies; and
- a second contact connected to the gate lead-out layer.
5. The semiconductor device according to claim 4, wherein the plurality of first columnar bodies are located in a device region of the semiconductor device, and the second contact is located in a terminal region of the semiconductor device.
6. The semiconductor device according to claim 5, wherein the second columnar body is in the terminal region of the semiconductor device.
7. The semiconductor device according to claim 1, wherein the second conductive layer follows the shape of the outer periphery of the plurality of first columnar bodies.
8. The semiconductor device according to claim 1, wherein the gate layer extends as a stripe between two adjacent first columnar bodies among the plurality of the first columnar bodies.
9. The semiconductor device according to claim 1, wherein the gate layer extends as a stripe between a plurality of adjacent first columnar bodies.
10. The semiconductor device according to claim 1, wherein the spacing between the gate layer and an adjacent first columnar body is constant.
11. The semiconductor device according to claim 1, wherein the shape of each of the plurality of the first columnar bodies is the same, and is at least one of a rectangular, a circular, or a regular hexagonal shape.
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Type: Grant
Filed: Aug 31, 2018
Date of Patent: Jul 7, 2020
Patent Publication Number: 20190296116
Assignees: KABUSHIKI KAISHA TOSHIBA (Tokyo), TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION (Tokyo)
Inventors: Hiroshi Matsuba (Fujisawa Kanagawa), Hung Hung (Kawasaki Kanagawa), Tatsuya Nishiwaki (Nonoichi Ishikawa), Kikuo Aida (Nomi Ishikawa), Kohei Oasa (Nonoichi Ishikawa)
Primary Examiner: Eric A. Ward
Application Number: 16/119,983
International Classification: H01L 29/78 (20060101); H01L 29/40 (20060101);