Abstract: A semiconductor device includes a semiconductor substrate; an anode electrode, formed on a surface on one side of the semiconductor substrate; a cathode electrode, formed on a surface on the other side of the semiconductor substrate; a P layer, formed on the anode electrode side in the semiconductor substrate; and an N layer, formed on the cathode electrode side in the semiconductor substrate and on the other side of the P layer. The cathode electrode and the N layer are Schottky functioned, the cathode electrode is a metal having work function ranging from 4.2 to 4.3, and the carrier concentration of the N layer ranges from 1×e12 to 1×e18/cm3.

Abstract: Problems with a conventional mesa type semiconductor device, which are deterioration in a withstand voltage and occurrence of a leakage current caused by reduced thickness of an insulation film on an inner wall of a mesa groove corresponding to a PN junction, are solved using an inexpensive material, and a mesa type semiconductor device of high withstand voltage and high reliability is offered together with its manufacturing method. A stable protection film made of a thermal oxide film is formed on the inner wall of the mesa groove in the mesa type semiconductor device to cover and protect the PN junction, and an insulation film having negative electric charges is formed to fill a space in the mesa groove covered with the thermal oxide film so that an electron accumulation layer is not easily formed at an interface between an N? type semiconductor layer and the thermal oxide film.

Abstract: This invention is directed to solving problems with a mesa type semiconductor device, which are deterioration in a withstand voltage and occurrence of a leakage current caused by reduced thickness of a second insulation film on an inner wall of a mesa groove corresponding to a PN junction, and offers a mesa type semiconductor device of high withstand voltage and high reliability and its manufacturing method. After the mesa groove is formed by dry-etching, wet-etching with an etching solution including hydrofluoric acid and nitric acid is further applied to a sidewall of the mesa groove to form an overhang made of the first insulation film above an upper portion of the mesa groove. The overhang serves as a barrier to prevent the second insulation film formed in the mesa groove and on the first insulation film around the mesa groove beyond an area of the overhang from flowing toward a bottom of the mesa groove due to an increased fluidity resulting from a subsequent thermal treatment.

Abstract: In a power MOS transistor, for example, a source electrode is formed so as to be commonly connected to a plurality of source regions formed on the front surface. Thus, a current density varies based on in-plane resistance of the source electrode, thereby providing the necessity of increasing the number of wires connecting the sources and a lead. In the invention, an electrode structure includes a copper plating layer 10e formed on a pad electrode 10a by an electrolytic plating method, and a nickel plating layer 10f and a gold plating layer formed so as to cover the upper and side surfaces of the copper plating layer 10e by an electroless plating method.

Abstract: A method of solidifying and detoxifying a soil, incinerated ash and coal ash to yield a solidified substance detoxified to a level complying with the environmental standards and a method of detoxifying polluted water containing dioxins and polluted water containing PCB are provided. First solidifying and detoxifying agent contains light burnt magnesite as component (1) and chrysolite powder as component (2), in which a ratio by weight of the component (1) and the component (2) is 1:5 to 5:1, preferably 1:3 to 3:1, more preferably 1:2 to 2:1 and is the solidifying and detoxifying agent applied to one kind selected from soil, incinerated ash and coal ash as well as polluted water containing dioxins and polluted water containing PCB. Other solidifying and detoxifying agent further contains as an additional component a fused phosphate fertilizer and titanium dioxide powder as well as anhydrous gypsum powder, light burnt dolomite and/or calcined lime powder.

Abstract: Provided are a semiconductor device and a method of manufacturing the same. In semiconductor devices of the conventional technologies, the chip size is increased when a breakdown voltage is increased. In the semiconductor device of this invention, an end of a pn junction interface (5) of a collector region (2) and a base region (3) is formed of a mesa groove (6) made of a trench. Thus, the chip size is not increased even when the mesa groove (6) is deeply formed to increase the breakdown voltage.

Abstract: A punch-through type IGBT generally has a thick p++-type collector layer. Therefore, the FWD need be externally attached to the IGBT when the IGBT is used as a switching element in an inverter circuit for driving a motor load, and thus the number of processes and components increases. In the invention, trenches are formed penetrating through a collector layer and reaching a buffer layer. A collector electrode is formed in the trenches, too. With this structure, a current path is formed between an emitter electrode and the collector electrode without through the collector layer and functions as the FWD.

Abstract: In a power MOS transistor, for example, a source electrode is formed so as to be commonly connected to a plurality of source regions formed on the front surface. Thus, a current density varies based on in-plane resistance of the source electrode, thereby providing the necessity of increasing the number of wires connecting the sources and a lead. In the invention, an electrode structure includes a copper plating layer 10e formed on a pad electrode 10a by an electrolytic plating method, and a nickel plating layer 10f and a gold plating layer formed so as to cover the upper and side surfaces of the copper plating layer 10e by an electroless plating method.

Abstract: Problems with a conventional mesa type semiconductor device, which are deterioration in a withstand voltage and occurrence of a leakage current caused by reduced thickness of an insulation film on an inner wall of a mesa groove corresponding to a PN junction, are solved using an inexpensive material, and a mesa type semiconductor device of high withstand voltage and high reliability is offered together with its manufacturing method. A stable protection film made of a thermal oxide film is formed on the inner wall of the mesa groove in the mesa type semiconductor device to cover and protect the PN junction, and an insulation film having negative electric charges is formed to fill a space in the mesa groove covered with the thermal oxide film so that an electron accumulation layer is not easily formed at an interface between an N? type semiconductor layer and the thermal oxide film.

Abstract: This invention is directed to solving problems with a mesa type semiconductor device, which are deterioration in a withstand voltage and occurrence of a leakage current caused by reduced thickness of a second insulation film on an inner wall of a mesa groove corresponding to a PN junction, and offers a mesa type semiconductor device of high withstand voltage and high reliability and its manufacturing method. After the mesa groove is formed by dry-etching, wet-etching with an etching solution including hydrofluoric acid and nitric acid is further applied to a sidewall of the mesa groove to form an overhang made of the first insulation film above an upper portion of the mesa groove. The overhang serves as a barrier to prevent the second insulation film formed in the mesa groove and on the first insulation film around the mesa groove beyond an area of the overhang from flowing toward a bottom of the mesa groove due to an increased fluidity resulting from a subsequent thermal treatment.

Abstract: A method of solidifying and detoxifying a soil, incinerated ash and coal ash to yield a solidified substance detoxified to a level complying with the environmental standards and a method of detoxifying polluted water containing dioxins and polluted water containing PCB are provided. First solidifying and detoxifying agent contains light burnt magnesite as component (1) and chrysolite powder as component (2), in which a ratio by weight of the component (1) and the component (2) is 1:5 to 5:1, preferably 1:3 to 3:1, more preferably 1:2 to 2:1 and is the solidifying and detoxifying agent applied to one kind selected from soil, incinerated ash and coal ash as well as polluted water containing dioxins and polluted water containing PCB. Other solidifying and detoxifying agent further contains as an additional component a fused phosphate fertilizer and titanium dioxide powder as well as anhydrous gypsum powder, light burnt dolomite and/or calcined lime powder.

Abstract: The invention realizes IGBT having an NPT structure which has a smaller variation in switching characteristics and the like and lower on-resistance. In the IGBT of the invention, by setting a ratio of a width of a trench to an interval between the trenches within a range of 1 to 2, electron current density and a conductivity modulation effect are optimized, a breakdown voltage is secured, a variation in characteristics is minimized, and on-resistance is largely reduced.

Abstract: In a conventional semiconductor device, there was a problem that, in a guard ring region, a shape of a depletion layer is distorted and stable withstand voltage characteristics cannot be obtained. In a semiconductor device of the present invention, a thermal oxide film in an actual operation region and a thermal oxide film in a guard ring region are formed in the same process. Thereafter, the thermal oxide film is once removed and is formed again. Thus, a film thickness of the thermal oxide film on the upper surface of the guard ring region is set to, for example, about 8000 to 10000 ?. Accordingly, a CVD oxide film including moving ions is formed in a position distant from a surface of an epitaxial layer. Consequently, distortion of a depletion layer, which is influenced by the moving ions, is suppressed and desired withstand voltage characteristics can be maintained.

Abstract: A punch-through type IGBT generally has a thick p++-type collector layer. Therefore, the FWD need be externally attached to the IGBT when the IGBT is used as a switching element in an inverter circuit for driving a motor load, and thus the number of processes and components increases. In the invention, trenches are formed penetrating through a collector layer and reaching a buffer layer. A collector electrode is formed in the trenches, too. With this structure, a current path is formed between an emitter electrode and the collector electrode without through the collector layer and functions as the FWD.

Abstract: There is the need to grind a semiconductor substrate from its back surface in order to thin a drift region for forming the NPT type IGBT. A collector region is then formed on the back surface of the semiconductor substrate by performing ion-implantation, a heat treatment and the like to the back surface of the semiconductor substrate of which the strength is weakened. This causes problems of warping the semiconductor substrate and the like. In a method of manufacturing a semiconductor device of the invention, the thickness of a drift region is previously adjusted by the thickness of an epitaxial layer. A collector region is then formed only by grinding a semiconductor substrate. In particular, using a semiconductor substrate containing a low concentration of impurity provides preferable characteristics for a high-speed switching element with a short turn-off time even when the collector region is thick.

Abstract: Thinning a semiconductor substrate has been needed for reducing on-resistance in a semiconductor device such as a vertical MOS transistor, IGBT, or the like where a high current flows in the semiconductor substrate in a vertical direction. In this case, the thinning is performed to the extent that the semiconductor substrate does not warp with a heat treatment, so that there is a limitation in reduction of on-resistance. In the invention, openings such as trench holes are formed on a back surface side of a semiconductor substrate. Then, a drain electrode is formed being electrically connected with bottoms of these openings. In this case, a current path is formed short corresponding to the depths of the openings, thereby easily achieving low on-resistance.

Abstract: In the present invention, in a pattern in which gate electrodes are provided in a stripe shape and source regions are provided in a ladder shape, body regions are provided in a stripe shape parallel to the gate electrodes. A first body region is exposed to a surface of a channel layer between first source regions adjacent to the gate electrode, and a second body region is provided below a second source region which connects the first source regions to each other. Thus, avalanche resistance can be improved. Moreover, since a mask for forming the body region is no longer required, there is a margin in accuracy of alignment.

Abstract: In a conventional semiconductor device, there was a problem that, in a guard ring region, a shape of a depletion layer is distorted and stable withstand voltage characteristics cannot be obtained. In a semiconductor device of the present invention, a thermal oxide film in an actual operation region and a thermal oxide film in a guard ring region are formed in the same process. Thereafter, the thermal oxide film is once removed and is formed again. Thus, a film thickness of the thermal oxide film on the upper surface of the guard ring region is set to, for example, about 8000 to 10000 ?. Accordingly, a CVD oxide film including moving ions is formed in a position distant from a surface of an epitaxial layer. Consequently, distortion of a depletion layer, which is influenced by the moving ions, is suppressed and desired withstand voltage characteristics can be maintained.

Abstract: A semiconductor device includes a power supply semiconductor chip that has a plurality of current passing electrodes and a plurality of control electrodes. Conductive plates are disposed on the current electrodes and the control electrodes, and extend to regions for external connections. The conductive plates also includes connecting regions that are suspended between the chip and the external connection regions and suppers vibration propagating to the chip. One conductive plate unit for the current passing electrodes and another conductive plate unit for the control electrodes are separately soldered on the corresponding electrodes. Alternatively, only one unit may be soldered on the semiconductor chip, and portions of the unit may be removed to fabricate the device. Because of the absence of wire-bonding steps, the semiconductor chip does not receive impact of wire-bonding during the manufacturing process.

Abstract: In conventional semiconductor devices, there observed a problem that cells on the devices may not function uniformly because of voltage drop in a main wiring layer due to a uniform and narrow width of the main wiring layer through which a main current flows. In a semiconductor device of the present invention, a width of one end of a main wire for carrying the main current is formed wider than a width of another end of the main wire. An overall width of the main wire is formed so as to be gradually narrowed from the one end to the another end. In this way, it is possible to reduce a difference in drive voltages between a cell located in the vicinity of an electrode pad for carrying the main current and a cell located in a remote position. Resultantly, it is possible to suppress a voltage drop in the main wire and to achieve uniform operations of cells in an element.