Patents by Inventor Kikuo Yamabe
Kikuo Yamabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8034179Abstract: In order to form an insulating film, which constitutes a flat interface with silicon, by CVD, a surface of silicon is oxidized to form a silicon oxide film using a plasma treatment apparatus in which microwaves are introduced into a chamber through a flat antenna having a plurality of holes. A silicon oxide film is formed as an insulating film on the silicon oxide film by CVD. Further, in the plasma treatment apparatus, a treating gas containing a noble gas and oxygen is introduced into the chamber, and, further, microwaves are introduced into the chamber through the flat antenna. Plasma is generated under a pressure in the range of not less than 6.7 Pa and not more than 533 Pa to modify the insulating film with the plasma.Type: GrantFiled: February 6, 2009Date of Patent: October 11, 2011Assignee: Tokyo Electron LimitedInventors: Yoshiro Kabe, Junichi Kitagawa, Kikuo Yamabe
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Patent number: 8026187Abstract: To form a good quality silicon oxide film provided with both a superior Qbd characteristic and Rd characteristic, a wafer W is loaded into a plasma treatment apparatus where the surface of a silicon layer 501 of the wafer W is treated by plasma oxidation to form on the silicon layer 501 to a film thickness T1 a silicon oxide film 503. Next, the wafer W on which the silicon oxide film 503 is formed is transferred to a thermal oxidation treatment apparatus where the silicon oxide film 503 is treated by thermal oxidation to thereby form a silicon oxide film 505 having a target film thickness T2.Type: GrantFiled: August 31, 2009Date of Patent: September 27, 2011Assignees: Tokyo Electron Limited, University of TsukubaInventors: Yoshiro Kabe, Junichi Kitagawa, Kikuo Yamabe
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Publication number: 20110039418Abstract: In order to form an insulating film, which constitutes a flat interface with silicon, by CVD, a surface of silicon is oxidized to form a silicon oxide film using a plasma treatment apparatus in which microwaves are introduced into a chamber through a flat antenna having a plurality of holes. A silicon oxide film is formed as an insulating film on the silicon oxide film by CVD. Further, in the plasma treatment apparatus, a treating gas containing a noble gas and oxygen is introduced into the chamber, and, further, microwaves are introduced into the chamber through the flat antenna. Plasma is generated under a pressure in the range of not less than 6.7 Pa and not more than 533 Pa to modify the insulating film with the plasma.Type: ApplicationFiled: February 6, 2009Publication date: February 17, 2011Applicant: TOKYO ELECTRON LIMITEDInventors: Yoshiro Kabe, Junichi Kitagawa, Kikuo Yamabe
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Publication number: 20100184267Abstract: To form a good quality silicon oxide film provided with both a superior Qbd characteristic and Rd characteristic, a wafer W is loaded into a plasma treatment apparatus where the surface of a silicon layer 501 of the wafer W is treated by plasma oxidation to form on the silicon layer 501 to a film thickness T1 a silicon oxide film 503. Next, the wafer W on which the silicon oxide film 503 is formed is transferred to a thermal oxidation treatment apparatus where the silicon oxide film 503 is treated by thermal oxidation to thereby form a silicon oxide film 505 having a target film thickness T2.Type: ApplicationFiled: August 31, 2009Publication date: July 22, 2010Applicants: TOKYO ELECTRON LIMITED, University of TsukubaInventors: Yoshiro Kabe, Junichi Kitagawa, Kikuo Yamabe
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Patent number: 6185472Abstract: A semiconductor device manufacturing method capable of proceeding semiconductor device manufacturing processes according to predetermined schedules or while correcting them without testpieces is provided. The method includes the steps of collecting actually observed data during at least one of plural steps, obtaining prediction data in at least one of plural steps by using an ab initio molecular dynamics process simulator or a molecular dynamics simulator, comparing and verifying the prediction data and the actually observed data sequentially at real time, and correcting and processing the plural manufacturing process factors sequentially at real time if a difference in significance is recognized between set values for the plural manufacturing process factors and the plural manufacturing process factors estimated from the actually observed data according to comparison and verification.Type: GrantFiled: December 27, 1996Date of Patent: February 6, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Shinji Onga, Takako Okada, Hiroshi Tomita, Kikuo Yamabe, Haruo Okano
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Patent number: 5885905Abstract: A method of processing a semiconductor substrate includes the step of subjecting a semiconductor substrate to a heat treatment under a gaseous atmosphere. The method comprises the step of subjecting a semiconductor substrate to a heat treatment at temperatures not lower than 1100.degree. C. under a non-oxidizing atmosphere, wherein heat treatments before said heat treatment applied to the semiconductor substrate are applied under heat treating temperatures and heat treating time which fall within a region defined by a line connecting four points of (900.degree. C., 4 minutes), (800.degree. C., 40 minutes), (700.degree. C., 11 hours) and (600.degree.0 C., 320 hours) in a graph, in which the heat treating temperature is plotted on the abscissa and the heat treating time is plotted on the ordinate of the graph.Type: GrantFiled: January 4, 1996Date of Patent: March 23, 1999Assignee: Kabushiki Kaisha ToshibaInventors: Souichi Nadahara, Kikuo Yamabe, Hideyuki Kobayashi, Kunihiro Terasaka, Akihito Yamamoto, Naohiko Yasuhisa
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Patent number: 5757063Abstract: A semiconductor device includes a semiconductor substrate having first and second main surfaces and including a denuded zone, in which an oxygen concentration is lower than that in an inner portion of the semiconductor substrate and which does not include a bulk microdefect, and an intrinsic gettering zone, and element region formed on the first surface of the semiconductor substrate, and an extrinsic gettering layer, made of an amorphous semiconductor material which traps a metal impurity, and formed directly on at least a portion of the intrinsic gettering region or the denuded zone entirely or partially thinned of the second main surface of the semiconductor substrate.Type: GrantFiled: October 11, 1996Date of Patent: May 26, 1998Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Tomita, Mami Takahashi, Kikuo Yamabe
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Patent number: 5698891Abstract: A semiconductor device includes a semiconductor substrate having first and second main surfaces and including a denuded zone, in which an oxygen concentration is lower than that in an inner portion of the semiconductor substrate and which does not include a bulk microdefect, and an intrinsic gettering zone, an element region formed on the first surface of the semiconductor substrate, and an extrinsic gettering layer, made of an amorphous semiconductor material which traps a metal impurity, and formed directly on at least a portion of the intrinsic gettering region or the denuded zone entirely or partially thinned of the second main surface of the semiconductor substrate.Type: GrantFiled: June 20, 1996Date of Patent: December 16, 1997Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Tomita, Mami Saito, Kikuo Yamabe
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Patent number: 5543334Abstract: A method of screening a semiconductor device. A silicon wafer having gate electrodes formed on the gate oxide film is prepared. An insulating layer is deposited on the silicon wafer. Gate electrode portions of a group of transistors to be tested are exposed. A conductive layer is deposited on the silicon wafer having exposed gate electrodes. The conductive layer is patterned to be a wiring layer so that the gate electrodes of a group of the transistors can be electrically connected to each other. The chip area to be tested is irradiated with light having intensity enough to generate a required quantity of carriers in a depletion layer between a well and a substrate. A predetermined test voltage is applied between the wiring layer and the substrate of the silicon wafer during irradiation of the light to measure current flowing through the wiring layer and the gate oxide film. An abnormality of the gate oxide film can be detected on the basis of the measured current value.Type: GrantFiled: December 15, 1994Date of Patent: August 6, 1996Assignee: Kabushiki Kaisha ToshibaInventors: Ichiro Yoshii, Hiroyuki Kamijoh, Yoshio Ozawa, Kikuo Yamabe, Kazuhiko Hashimoto, Katsuya Okumura, Kaoru Hama
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Patent number: 5514904Abstract: A semiconductor device includes a monocrystalline silicon substrate, an insulating film consisting of a monocrystalline silicon oxide formed on the surface of the monocrystalline silicon substrate, and a conductive film formed on the insulating film. The monocrystalline silicon substrate has a (100) plane orientation, the insulating film essentially consists of .beta.-cristobalite having a unit structure in a P4.sub.1 2.sub.1 2 structural expression in such a manner that every other silicon atoms of four silicon atoms aligned about a C-axis are arranged on two adjacent silicon atoms aligned in a 110! direction on an Si (100) plane, and that a plane including the C-axis of the .beta.-cristobalite and the 110! direction is set perpendicular to the (100) plane.Type: GrantFiled: August 26, 1994Date of Patent: May 7, 1996Assignee: Kabushiki Kaisha ToshibaInventors: Shinji Onga, Takako Okada, Kouichirou Inoue, Yoshiaki Matsushita, Kikuo Yamabe, Hiroaki Hazama, Haruo Okano
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Patent number: 5502010Abstract: A method of processing a semiconductor substrate includes the step of subjecting a semiconductor substrate to a heat treatment under a gaseous atmosphere. The method comprises the step of subjecting a semiconductor substrate to a high temperature heat treatment at temperatures not lower than 1100.degree. C. under a non-oxidizing atmosphere, wherein heat treatments before the high temperature heat treatment applied to the semiconductor substrate are applied under heat treating temperatures and heat treating time which fall within a region defined by a line connecting four points of (900.degree. C., 4 minutes), (800.degree. C., 40 minutes), (700.degree. C., 11 hours) and (600.degree. C., 320 hours) in a graph, in which the heat treating temperature is plotted on the abscissa and the heat treating time is plotted on the ordinate of the graph.Type: GrantFiled: July 15, 1993Date of Patent: March 26, 1996Assignee: Kabushiki Kaisha ToshibaInventors: Souichi Nadahara, Kikuo Yamabe, Hideyuki Kobayashi, Kunihiro Terasaka, Akihito Yamamoto, Naohiko Yasuhisa
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Patent number: 5489542Abstract: A method for fabricating a semiconductor device on a silicon substrate, consists of producing a silicon oxide film on the silicon substrate producing a thin silicon nitride film on the silicon oxide film, thermally nitriding the silicon nitride film in an atmosphere of nitrogenous gas, producing a conductive film on the silicon nitride film nitrided in the atmosphere of the nitrogenous gas, producing a gate region from the silicon oxide film, the silicon nitride film, and the conductive film, a channel region being positioned under the gate region in the silicon substrate, producing a source region in the silicon substrate adjacent to one side of the channel region, producing a drain region in the silicon substrate adjacent to another side of the channel region, and producing wiring regions on the source region, the drain region, and the gate region.Type: GrantFiled: July 16, 1993Date of Patent: February 6, 1996Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Iwai, Toyota Morimoto, Hisayo S. Momose, Kikuo Yamabe, Yoshio Ozawa
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Patent number: 5431561Abstract: A method and an apparatus for heat treating in a heat treating apparatus having a heating chamber to be introduced with predetermined gas, a heater disposed around the heating chamber, and jigs disposed in the heating chamber for supporting wafers of a plurality of substrates to be treated in parallel with each other, wherein in order to make the temperature distribution of the wafers of the substrates to be treated in the radial direction uniform in the heat treatment, the jigs are formed to determine the sizes and the shape thereof in predetermined ranges having a gradient according to the heat treating method having a predetermined shape determining procedure so that the jigs are formed in ring-shaped trays (i.e. support-ring) for holding at the peripheries the substrates to be treated and the thickness of the tray is constant or such that the outer peripheral side thereof is thicker than the inner peripheral side thereof.Type: GrantFiled: December 14, 1993Date of Patent: July 11, 1995Assignees: Kabushiki Kaisha Toshiba, Tokyo Electron Sagami LimitedInventors: Kikuo Yamabe, Keitaro Imai, Katsuya Okumura, Ken Nakao, Seikou Ueno
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Patent number: 5360748Abstract: A method of manufacturing a semiconductor device, which comprises the steps of providing a semiconductor substrate having a first primary surface which is designated to form the semiconductor device and a second primary surface opposite from the first primary surface, the substrate containing contaminants therein; forming a boron-doped layer on the second primary surface of the substrate; and absorbing the contaminants into the boron-doped layer.Type: GrantFiled: January 22, 1993Date of Patent: November 1, 1994Assignee: Kabushiki Kaisha ToshibaInventors: Soichi Nadahara, Kikuo Yamabe
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Patent number: 5354710Abstract: A method of manufacturing semiconductor devices comprises the steps of preparing a semiconductor substrate having a surface and a natural oxide film on the surface, forming an adsorption enhancement layer on the surface of the semiconductor substrate, forming an impurity adsorption layer containing impurities on the adsorption enhancement layer, and thermally diffusing the impurities through the adsorption enhancement layer and the natural oxide film into the substrate.Type: GrantFiled: February 12, 1993Date of Patent: October 11, 1994Assignee: Kabushiki Kaisha ToshibaInventors: Hideichi Kawaguchi, Yoshitaka Tsunashima, Kikuo Yamabe, Katsuya Okumura
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Patent number: 5297956Abstract: A method and an apparatus for heat treating in a heat treating apparatus having a heating chamber to be introduced with predetermined gas, a heater disposed around the heating chamber, and jigs disposed in the heating chamber for supporting wafers of a plurality of substrates to be treated in parallel with each other, wherein in order to make the temperature distribution of the wafers of the substrates to be treated in the radial direction uniform in the heat treatment, the jigs are formed to determine the sizes and the shape thereof in predetermined ranges having a gradient according to the heat treating method having a predetermined shape determining procedure so that the jigs are formed in ring-shaped trays (i.e. support-ring) for holding at the peripheries the substrates to be treated and the thickness of the tray is constant or such that the outer peripheral side thereof is thicker than the inner peripheral side thereof.Type: GrantFiled: November 29, 1991Date of Patent: March 29, 1994Assignees: Kabushiki Kaisha Toshiba, Tokyo Electron Sagami LimitedInventors: Kikuo Yamabe, Keitaro Imai, Katsuya Okumura, Ken Nakao, Seikou Ueno
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Patent number: 5259883Abstract: An apparatus for thermally processing semiconductor wafers within a reaction tube in which the wafers are thermally processed in a higher temperature region within the reaction tube. The thermally processed semiconductor waters are moved into a lower temperature region within the reaction tube. The rate of heat radiated from the thermally processed semiconductor waters is reduced in the lower temperature region within the reaction tube.Type: GrantFiled: March 5, 1993Date of Patent: November 9, 1993Assignee: Kabushiki Kaisha ToshibaInventors: Kikuo Yamabe, Katsuya Okumura
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Patent number: 5239614Abstract: A heat-treating method comprising preparing a plurality of wafers parallel to one another in a process tube while keeping their surfaces to be treated substantially horizontal, arranging plural MoSi.sub.2 wire heaters along the longitudinal axis of the process tube so as to be placed around the process tube, adjusting the amount of current supplied to the heaters to form on the treated surface of each of the wafers temperature gradient extending from one side of the outer circumferential rim of each of the wafers to the other side thereof, and rotating the wafers in their surfaces.Type: GrantFiled: November 14, 1991Date of Patent: August 24, 1993Assignees: Tokyo Electron Sagami Limited, Kabushiki Kaisha ToshibaInventors: Seiko Ueno, Ken Nakao, Kikuo Yamabe, Keitaro Imai
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Patent number: 5237188Abstract: A semiconductor device formed on a silicon substrate consisting of the steps of producing a silicon oxide film on the silicon substrate, producing a thin silicon nitride film on the silicon oxide film, thermally nitriding the silicon nitride film in an atmosphere of nitrogenous gas, producing a conductive film on the silicon nitride film nitrided in the atmosphere of the nitrogenous gas, producing a gate region from the silicon oxide film, the silicon nitride film, and the conductive film, a channel region being positioned under the gate region in the silicon substrate, producing a source region in the silicon substrate adjacent to one side of the channel region, producing a drain region in the silicon substrate adjacent to another side of the channel region, and producing wiring regions on the source region, the drain region, and the gate region.Type: GrantFiled: November 27, 1991Date of Patent: August 17, 1993Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Iwai, Toyota Morimoto, Hisayo S. Momose, Kikuo Yamabe, Yoshio Ozawa
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Patent number: 5189503Abstract: A dielectric insulation film consists of a metal oxide and pieces of dissimilar metal element added to the metal oxide. A positive charge number under an ionized state of the dissimilar metal element is smaller by one than that of the metal oxide. An ionic charge number of the dissimilar metal element is of a predetermined one kind. The dielectric insulation film is formed as an insulation film of capacitor of each cell of a semiconductor device according to a chemical vapor deposition (CVD) method in the process of forming cells of the semiconductor device.Type: GrantFiled: April 10, 1991Date of Patent: February 23, 1993Assignee: Kabushiki Kaisha ToshibaInventors: Kyoichi Suguro, Keitaro Imai, Mitsutoshi Koyama, Kikuo Yamabe