Patents by Inventor Kikuo Yamabe

Kikuo Yamabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5173440
    Abstract: In fabricating a semiconductor device, when impurities are diffused from a silicon oxide layer containing the impurities to a semiconductor layer, a diffusion atmosphere is controlled so as to oxidize or reduce a specified impurity to thereby control the diffusion coefficient of the impurities in the silicon oxide layer. Thus, it is possible to form a diffusion layer having a desired impurity profile under a good control.
    Type: Grant
    Filed: May 1, 1990
    Date of Patent: December 22, 1992
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshitaka Tsunashima, Kenji Todori, Kikuo Yamabe
  • Patent number: 5073813
    Abstract: A MOS structure is formed on a silicon semiconductor substrate surface using a first gate electrode film made of polysilicon, an element isolation groove reaching the inside of the silicon semiconductor substrate is formed, and an insulating film is filled in the groove. In addition, a second gate electrode film made of a refractory metal such as molybdenum silicide is formed to be connected to the first gate electrode film, and the first and second gate electrode films are simultaneously removed to form a MOS gate electrode and a wiring layer.
    Type: Grant
    Filed: July 26, 1990
    Date of Patent: December 17, 1991
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigeru Morita, Kikuo Yamabe, Masakazu Kakumu
  • Patent number: 4735824
    Abstract: A method of forming an MOS capacitor by the steps of cutting a groove in the surface of a silicon substrate by the RIE process, thermally oxidizing the surface of said silicon substrate, depositing a capacitor electrode on said capacitor-insulating layer, being characterized in that when the capacitor-insulating layer is deposited, the surface of the silicon substrate is thermally oxidized in an oxidizing atmosphere containing 15% by vol. of steam.
    Type: Grant
    Filed: May 23, 1986
    Date of Patent: April 5, 1988
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kikuo Yamabe, Keitaro Imai