Abstract: An ESD (Electro-Static Discharge) protection circuit includes a detection unit for detecting a rising time of a signal flowing into a first and a second power lines; a pre-driver for buffering an output signal of the detection unit; and a power clamp which operates in response to an output signal of the pre-driver and connects the first and the second power lines each other. The detection unit includes: an RC filter connected in series between the first and the second power lines; a first inverter for inverting an output of the RC filter; and a first capacitor, connected between the first power line and a source end of a first transistor of the first inverter, for preventing a leakage current from flowing through the first transistor and a second transistor of the first inverter when a power noise is applied to the first and the second power lines.

Abstract: An ESD protection circuit using an N-type extended drain silicon controlled rectifier (N-EDSCR) and a method for fabricating the same are provided. An electro-static discharge (ESD) protection circuit includes a substrate, a well formed in the substrate, a drift region having a predetermined portion overlapped with the well, a plurality of first diffusion layers respectively formed in the well and the drift region, a plurality of second diffusion layers respectively formed in the well and the drift region, wherein corresponding first and second diffusion layers in the well are formed separately from each other and those in the drift region are formed adjacent to each other, a source region formed in a manner of surrounding a second conductive type diffusion layer inside the well, and a gate electrode formed on the well between the source and the drift region.

Abstract: A high voltage operating electrostatic discharge protection device is provided. The high voltage operating electrostatic discharge protection device includes: a first gate structure and a second gate structure disposed on a substrate of a first conductive type with a predetermined distance; a well of the first conductive type formed in a first region of the substrate such that the well contacts one bottom portion of the first gate structure; a source region of a second conductive type formed within in the well; a counter pocket source region of the first conductive type formed within the well encompassing the source region; and a drift region of the second conductive type contacting a bottom surface of the second gate structure and formed in a second region of the substrate such that the drift region contacts the other bottom portion of the first gate structure.

Abstract: Disclosed herein are a device for electrostatic protection and circuit thereof.

Abstract: The present invention relates to a device for electrostatic discharge protection (ESD).

Abstract: An electrostatic discharge (ESD) protection device is provided. The apparatus includes: a double diffused drain N-type metal oxide semiconductor field effect transistor (MOSFET); a P-type silicon controlled rectifier (SCR); a double diffused drain P-type MOSFET; and an N-type SCR, wherein: the double diffused drain N-type MOSFET is connected in parallel with the P-type SCR between an output pad and a first voltage pad; the double diffused drain P-type MOSFET is connected in parallel with the N-type SCR between the output pad and a second voltage pad; and the N-type SCR is connected in parallel with the P-type SCR between the first voltage pad and the second voltage pad.

Abstract: An ESD (Electro-Static Discharge) protection circuit includes a detection unit for detecting a rising time of a signal flowing into a first and a second power lines; a pre-driver for buffering an output signal of the detection unit; and a power clamp which operates in response to an output signal of the pre-driver and connects the first and the second power lines each other. The detection unit includes: an RC filter connected in series between the first and the second power lines; a first inverter for inverting an output of the RC filter; and a first capacitor, connected between the first power line and a source end of a first transistor of the first inverter, for preventing a leakage current from flowing through the first transistor and a second transistor of the first inverter when a power noise is applied to the first and the second power lines.

Abstract: The present invention relates to a device for electrostatic discharge protection (ESD).

Abstract: An ESD protection circuit using an N-type extended drain silicon controlled rectifier (N-EDSCR) and a method for fabricating the same are provided. An electro-static discharge (ESD) protection circuit includes a substrate, a well formed in the substrate, a drift region having a predetermined portion overlapped with the well, a plurality of first diffusion layers respectively formed in the well and the drift region, a plurality of second diffusion layers respectively formed in the well and the drift region, wherein corresponding first and second diffusion layers in the well are formed separately from each other and those in the drift region are formed adjacent to each other, a source region formed in a manner of surrounding a second conductive type diffusion layer inside the well, and a gate electrode formed on the well between the source and the drift region.

Abstract: A surface light source device includes a light source body having a plurality of discharge spaces that are divided into a light-emitting region and a non-light-emitting region. The light-emitting region has a first cross sectional area. The non-light-emitting region has a second cross sectional area larger than the first cross sectional area. An electrode for applying a voltage to a discharge gas, which is injected into the discharge spaces, is provided to a portion of the light source body corresponding to the non-light-emitting region. Thus, a larger amount of the discharge gas may be distributed in the non-light-emitting region than in the light-emitting region. As a result, the electrode may not serve as a dark field. Further, the surface light source device may have a long life span.

Abstract: An air cleaner with aroma generation is disclosed.

Abstract: An electrostatic discharge (ESD) protection device is provided. The apparatus includes: a double diffused drain N-type metal oxide semiconductor field effect transistor (MOSFET); a P-type silicon controlled rectifier (SCR); a double diffused drain P-type MOSFET; and an N-type SCR, wherein: the double diffused drain N-type MOSFET is connected in parallel with the P-type SCR between an output pad and a first voltage pad; the double diffused drain P-type MOSFET is connected in parallel with the N-type SCR between the output pad and a second voltage pad; and the N-type SCR is connected in parallel with the P-type SCR between the first voltage pad and the second voltage pad.

Abstract: A high voltage operating electrostatic discharge protection device is provided. The high voltage operating electrostatic discharge protection device includes: a first gate structure and a second gate structure disposed on a substrate of a first conductive type with a predetermined distance; a well of the first conductive type formed in a first region of the substrate such that the well contacts one bottom portion of the first gate structure; a source region of a second conductive type formed within in the well; a counter pocket source region of the first conductive type formed within the well encompassing the source region; and a drift region of the second conductive type contacting a bottom surface of the second gate structure and formed in a second region of the substrate such that the drift region contacts the other bottom portion of the first gate structure.

Abstract: The present invention relates to a semiconductor device and a method of fabricating the same for simplifying a fabrication process of the semiconductor device and enhancing the performance and yield of the device. A first metal wiring on a semiconductor substrate serves as a first electrode of a metal-insulator-metal (MIM) capacitor. A dielectric film pattern is formed on the first metal wiring. A first via-contact plug on the dielectric film pattern contacts a side of the first metal wiring. An interlayer insulation film is formed having second via-contact plugs in a parallel array structure. The second via-contact plugs contact the dielectric film pattern and serve as a second electrode of the MIM capacitor. A second metal wiring is formed on the interlayer insulation film to contact the first via-contact plug and the second via-contact plugs.

Abstract: A method for forming a metal line of an Al/Cu structure is disclosed. In a state where a first Ti/TiN layer, an Al layer, and a second Ti/TiN layer are layered, the grooves are formed by etching the upper half the Al layer using a photoresist film, which is formed on the second Ti/TiN layer by a negative patterning process, as a mask. After a third Ti/TiN layer and a Cu layer are formed in the grooves, the third Ti/TiN (buffer) layer, the second Ti/TiN layer, the Al layer, and the first Ti/TiN layer are etched using the Cu layer as a mask. Thus, the metal line having a layered structure of the first Ti/TiN layer, the Al layer, the third Ti/TiN layer, and the Cu layer is formed. In such case, since thickness of the photoresist film has decreased by half the thickness of the Al layer, the photoresist film can finely be patterned.

Abstract: The present invention relates to a semiconductor device and a method of fabricating the same for simplifying a fabrication process of the semiconductor device and enhancing the performance and yield of the device. A first metal wiring on a semiconductor substrate serves as a first electrode of a metal-insulator-metal (MIM) capacitor. A dielectric film pattern is formed on the first metal wiring. A first via-contact plug on the dielectric film pattern contacts a side of the first metal wiring. An interlayer insulation film is formed having second via-contact plugs in a parallel array structure. The second via-contact plugs contact the dielectric film pattern and serve as a second electrode of the MIM capacitor. A second metal wiring is formed on the interlayer insulation film to contact the first via-contact plug and the second via-contact plugs.

Abstract: A method for forming a dual damascene line structure includes forming an inter-metal dielectric including a first region and a second region on a semiconductor substrate, forming a first hard mask material layer on an entire surface of the inter-metal dielectric, removing the first hard mask material layer on the first region, forming a second hard mask material layer on an entire surface of the inter-metal dielectric, forming a hard mask to remove a portion of the first hard mask material layer on the second region, etching the inter-metal dielectric of the first region to a first thickness using the hard mask, exposing the inter-metal dielectric of the second region, and etching the exposed inter-metal dielectric to simultaneously form a via hole and a trench having the via hole.

Abstract: The present invention relates to a transistor of a semiconductor and a method of fabricating the same. In the method, the dual gate electrode may have different widths and is formed using a damascene process. The dual gate electrode is formed using a stacked upper having a first gate electrode and a second gate electrode. The second gate electrode may have a broader width than the lower first gate electrode.

Abstract: The present invention relates to a semiconductor device and a method of fabricating the same for simplifying a fabrication process of the semiconductor device and enhancing the performance and yield of the device. A first metal wiring on a semiconductor substrate serves as a first electrode of a metal-insulator-metal (MIM) capacitor. A dielectric film pattern is formed on the first metal wiring. A first via-contact plug on the dielectric film pattern contacts a side of the first metal wiring. An interlayer insulation film is formed having second via-contact plugs in a parallel array structure. The second via-contact plugs contact the dielectric film pattern and serve as a second electrode of the MIM capacitor. A second metal wiring is formed on the interlayer insulation film to contact the first via-contact plug and the second via-contact plugs.

Abstract: The present invention relates to a transistor of a semiconductor and a method of fabricating the same. In the method, the dual gate electrode may have different widths and is formed using a damascene process. The dual gate electrode is formed using a stacked upper having a first gate electrode and a second gate electrode. The second gate electrode may have a broader width than the lower first gate electrode.