Abstract: A reticle structure and a method of forming a photoresist profile on a substrate using the reticle having a multi-level profile. The reticle comprises (1) a transparent substrate, (2) a partially transmitting 180 degree phase shift film overlying predetermined areas of the transparent substrate to transmit approximately 20 to 70% of incident light, and (3) an opaque film overlying the predetermined areas of the partially transmitting 180 degree phase shift film. The method comprises the following steps: a) depositing a photoresist film over the substrate; b) directing light to the photoresist film through the reticle, and c) developing the photoresist film to form an opening in the resist layer where light only passed thru the substrate, and to remove intermediate thickness of the photoresist film, in the areas where the light passed through the partially transmitting 180 degree phase shift film. In an aspect, the photoresist film is comprised of a lower photoresist layer and an upper photoresist layer.

Abstract: Providing ASIC equivalents of FPGAs is facilitated and made more efficient and economical by using an ASIC architecture including a plurality of so-called hybrid logic elements (“HLEs”), each of which can provide a portion of the full functionality of an FPGA logic element (“LE”). The functionality of each FPGA LE implementing a user's logic design can be mapped to one or more HLEs without re-synthesis of the user's logic. Only as many HLEs as are necessary are used to perform the functions of each LE. The one-for-one equivalence between each LE and either (1) one HLE or (2) a group of HLEs facilitates mapping (without re-synthesis) in either direction between FPGA and ASIC designs.

Abstract: There is disclosed a system and method for increasing heat dissipation of LED displays by using the current PCB packaging mounted to a LCD panel support structure thereby eliminating the need for a metal core PCB. In one embodiment, reverse mounted LEDs having heat dissipation pads are used to optimize heat transfer to a metal layer which is then placed in contact with the LCD support structure.

Abstract: An oblique angle deposition is used to provide an A-plate optical retarder having at least one dense, form-birefringent layer. According to one embodiment, the dense, form-birefringent layer(s) are deposited as part of an FBAR stack to provide an all-dielectric full-function A/?C-plate trim retarder for LCD birefringence compensation. Advantageously, the dense structure of the full-function A/?C-plate trim retarder offers high durability and/or stability, thus making it well suited for providing polarization compensation in high light flux polarization-based projection systems.

Abstract: A manufacturing method of a semiconductor device with a copper redistribution line, a copper inductor and aluminum wire bond pads and the integration of the resulting device with an integrated circuit on a single chip, resulting in the decreased size of the chip.

Abstract: A phase shifting photolithography system includes inserting a phase shift component in a path of an illumination, wherein the phase shift component modifies a portion of the of the illumination to a different, and controlling an aperture shutter of the phase shift component modifying an interference of the illumination and the illumination with the different phase.

Abstract: A polarizing photolithography reticle system is provided including providing a reticle substrate, forming polarization structures on the reticle substrate, and etching circuit patterns on the reticle substrate on a side opposite the polarization structures.

Abstract: The invention relates to a method of electronic contrast enhancement for an LCD panel for use in an imaging device. The method comprises the step of coupling the LCD panel with a trim retarder in a pre-determined azimuthal orientation for at least partially compensating the residual in-plane retardance, followed by the step of non-mechanical fine-tuning of a dark state of the LCD panel. In the preferred embodiment, the fine-tuning of the dark state of the LCD panel is realized by adjusting the dark-state magnitude of the LC voltage. The method can be used in batch, e.g. wafer-level manufacturing of integrated trim retarder/LCD panels assemblies that can be electronically tuned to provide high on/off contrast.

Abstract: A grating trim retarder fabricated from a form-birefringent multi-layer dielectric stack including at least one anti-reflection coating and supported on a transparent substrate is provided. The form-birefringent dielectric stack includes an axially-inhomogeneous element in the form of a ?C-plate grating and a transversely-inhomogeneous element in the form of an A-plate grating. Each of the ?C-plate and the A-plate gratings are fabricated with dimensions to form a zeroth order sub-wavelength grating structure. Fabricating the grating trim retarder with anti-reflection coatings and/or a segment where the ?C-plate and A-plate grating overlap enables the in-plane and out-of-plane retardances to be tailored independently according to the desired application.

Abstract: A trim retarder for a liquid crystal display based projection system including a light source, a polarizer/analyzer, a liquid crystal display panel, and a projection lens, is clocked to an optimal azimuthal angle that provides a system contrast level substantially unaffected by the orientation of the slow axis of the liquid crystal display panel.

Abstract: In one embodiment, an opto-electronic package includes a substrate, a cavity, mounting pads and transverse walls interspersed along the cavity, pads separated by transverse walls, and transverse walls being lower than cavity-defining walls; and LED dice mounted to the pads. In another embodiment, a system is disclosed for backlighting an LCD screen. The system includes an opto-electronic package having a substrate; LED dice mounted to the substrate; an encapsulant disposed over LED dice; and a light guide having an input portion to receive light provided by LED dice, the input portion in attachment to encapsulant, and an output portion configured to transmit light to LCD screen. In yet another embodiment, a method of manufacturing an opto-electronic package includes: fabricating a substrate; attaching LED dice to the substrate; electrically connecting each LED dice to an outer portion of the substrate; and disposing encapsulant over the LED dice.

Abstract: An integrated circuit is packaged, in one embodiment, by wire bonding to pads supported by tape. The tape also supports traces that run from the wire bonded location to a pad for solder balls. A heat spreader is thermally connected to the integrated circuit and is located not just in the area under the die but also extends to the edge of the package in the area outside the wire bonding location. This outer area is thermally connected to the area under the die by thermal bars that run between some of the wire bond locations. During the manufacturing of the package the heat spreader is connected to slotted rails by tie bars. During singulation, the tie bars are easily broken or sawed because they are significantly reduced in thickness from the thickness of the heat spreader as a whole.

Abstract: A C-plate compensator is disclosed for compensating the residual A-plate and C-plate retardance of a reflective liquid crystal on silicon (LCoS) display or a transmissive liquid crystal (LC) display in a projection display system. The C-plate incorporates a form-birefringent coating, whose retardance magnitude can be adjusted by tilting with respect to the display panel (X-Y) plane. The tilted plate is rotated about the Z-axis by a prescribed amount from the slow axis of the display panel. Criteria are described for choosing the tilt and rotation angles such that the contrast of the display system produced by the compensated panel is optimized.

Abstract: As part of a process for producing a structured ASIC that is functionally equivalent to an FPGA that has been programmed to perform a user's logic design, a compilation of that design that has been prepared for ASIC implementation is converted to a physical layout of the structured ASIC. The production of this physical layout honors timing constraints supplied by the user, and also preserves functional equivalence to the reference programmed FPGA. The structured ASIC can be manufactured from the physical layout produced.

Abstract: A semiconductor design is provided having at least one feature at one of a line end and a line junction, and phase regions. At least one cut line is added to at least one of such features at line ends and such features at line junctions. Phases are assigned to the phase regions. The manufacturing of a photomask with the assigned phase regions is directed.

Abstract: A structure, a method of fabricating and a method of using a phase shift mask (PSM) having a first phase shifted section, a half tone section, and a second phase shifted section. The first phase shift section and the half tone section are shifted 180 degrees with the second phase shift region. Embodiments provide for (1) a half tone, single trench alternating phase shift mask and (2) a half tone, dual trench alternating phase shift mask. The half tone region provides advantages over conventional alternating phase shift masks.

Abstract: Providing ASIC equivalents of FPGAs is facilitated and made more efficient and economical by using an ASIC architecture including a plurality of so-called hybrid logic elements (“HLEs”), each of which can provide a portion of the full functionality of an FPGA logic element (“LE”). The functionality of each FPGA LE implementing a user's logic design can be mapped to one or more HLEs without re-synthesis of the user's logic. Only as many HLEs as are necessary are used to perform the functions of each LE. The one-for-one equivalence between each LE and either (1) one HLE or (2) a group of HLEs facilitates mapping (without re-synthesis) in either direction between FPGA and ASIC designs.

Abstract: The present invention relates to trim retarders used to compensate for residual birefringence created by liquid crystal display panels. In particular the present invention relates to a trim retarder with negative out-of-plane birefringence provided by a form birefringent multi-layer dielectric stack for compensating for retardances resulting from liquid crystal on silicon display panels.

Abstract: The invention relates to a polarization compensating element (PCE) for a liquid crystal, e.g. liquid crystal on silicon (LCoS), display system manufactured using a linearly photo-polymerizable polymer (LPP) for orienting a photo-polymerizable liquid crystal polymer (LCP) film. To decrease the reflection, polarization conversion, and interference events in an LPP/LCP assembly the ?N birefringence value of the LCP material is minimized. Dielectric coatings are added at various locations throughout the assembly for minimizing the amount of reflection, polarization conversion, and interference effects and for suppressing spatial retardance ripples.

Abstract: A die, comprising a substrate and one or more pillar structures formed over the substrate in a pattern and the method of forming the die.