Patents by Inventor Kimball M. Watson
Kimball M. Watson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20110185330Abstract: An array of through substrate vias (TSVs) is formed through a semiconductor substrate and a contact-via-level dielectric layer thereupon. A metal-wire-level dielectric layer and a line-level metal wiring structure embedded therein are formed directly on the contact-via-level dielectric layer. The line-level metal wiring structure includes cheesing holes that are filled with isolated portions of the metal-wire-level dielectric layer. In one embodiment, the entirety of the cheesing holes is located outside the area of the array of the TSVs to maximize the contact area between the TSVs and the line-level metal wiring structure. In another embodiment, a set of cheesing holes overlying an entirety of seams in the array of TSVs is formed to prevent trapping of any plating solution in the seams of the TSVs during plating to prevent corrosion of the TSVs at the seams.Type: ApplicationFiled: April 6, 2011Publication date: July 28, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David S. Collins, Alvin Joseph, Peter J. Lindgren, Anthony K. Stamper, Kimball M. Watson
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Patent number: 7981732Abstract: A method for programming a laser fuse. The laser fuse has a fuse link including a material having a characteristic of changing its electrical resistance after being exposed to a laser beam. The laser beam is directed to the fuse link, the laser beam being controlled such that, in response to the impact of the laser beam upon the fuse link, the electrical resistance of the fuse link changes but the fuse link is not blown off.Type: GrantFiled: April 18, 2008Date of Patent: July 19, 2011Assignee: International Business Machines CorporationInventors: Dinesh A. Badami, Tom C. Lee, Baozhen Li, Gerald Matusiewicz, William T. Motsiff, Christopher D. Muzzy, Kimball M. Watson, Jean E. Wynne
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Patent number: 7968975Abstract: An array of through substrate vias (TSVs) is formed through a semiconductor substrate and a contact-via-level dielectric layer thereupon. A metal-wire-level dielectric layer and a line-level metal wiring structure embedded therein are formed directly on the contact-via-level dielectric layer. The line-level metal wiring structure includes cheesing holes that are filled with isolated portions of the metal-wire-level dielectric layer. In one embodiment, the entirety of the cheesing holes is located outside the area of the array of the TSVs to maximize the contact area between the TSVs and the line-level metal wiring structure. In another embodiment, a set of cheesing holes overlying an entirety of seams in the array of TSVs is formed to prevent trapping of any plating solution in the seams of the TSVs during plating to prevent corrosion of the TSVs at the seams.Type: GrantFiled: August 8, 2008Date of Patent: June 28, 2011Assignee: International Business Machines CorporationInventors: David S. Collins, Alvin Joseph, Peter J. Lindgren, Anthony K. Stamper, Kimball M. Watson
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Patent number: 7919830Abstract: A method for fabricating a low-value resistor such as a ballast resistor for bipolar junction transistors. The resistor may be fabricated using layers of appropriate sheet resistance so as to achieve low resistance values in a compact layout. The method may rely on layers already provided by a conventional CMOS process flow, such as contact plugs and fully silicided (FUSI) metal gates.Type: GrantFiled: April 3, 2008Date of Patent: April 5, 2011Assignee: International Business Machines CorporationInventors: Douglas D. Coolbaugh, Ebenezer E. Eshun, Zhong-Xiang He, Robert M. Rassel, Kimball M. Watson
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Patent number: 7919834Abstract: One or more multilayer back side metallurgy (BSM) stack structures are formed on thru-silicon-vias (TSV). The multiple layers of metal may include an adhesion layer of chromium on the semiconductor wafer back side, a conductive layer of copper, diffusion barrier layer of nickel and a layer of nobel metal, such as, gold. To prevent edge attack of copper after dicing, the layer of nickel is formed to seal the copper edge. To also prevent edge attack of the layer of nickel after dicing, the layer of gold is formed to seal both the layer of copper and the layer of nickel.Type: GrantFiled: December 4, 2007Date of Patent: April 5, 2011Assignee: International Business Machines CorporationInventors: Robert Edgar Davis, Robert Daniel Edwards, J. Edwin Hostetter, Jr., Ping-Chuan Wang, Kimball M. Watson
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Patent number: 7904273Abstract: A system, method and device for measuring a depth of a Through-Silicon-Via (TSV) in a semiconductor device region on a wafer during in-line semiconductor fabrication, includes a resistance measurement trench structure having length and width dimensions in a substrate, ohmic contacts on a surface of the substrate disposed on opposite sides of the resistance measurement trench structure, and an unfilled TSV structure in semiconductor device region having an unknown depth. A testing circuit makes contact with the ohmic contacts and measures a resistance therebetween, and a processor connected to the testing circuit calculates a depth of the trench structure and the unfilled TSV structure based on the resistance measurement. The resistance measurement trench structure and the unfilled TSV are created simultaneously during fabrication.Type: GrantFiled: February 16, 2009Date of Patent: March 8, 2011Assignee: International Business Machines CorporationInventors: Qizhi Liu, Ping-Chuan Wang, Kimball M. Watson, Zhijian J. Yang
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Patent number: 7904868Abstract: A design structure including a semiconductor structure. The semiconductor structure includes (a) a substrate; (b) a first semiconductor device on the substrate; (c) N ILD (Inter-Level Dielectric) layers on the first semiconductor device, wherein N is an integer greater than one; and (d) an electrically conductive line electrically coupled to the first semiconductor device. The electrically conductive line is adapted to carry a lateral electric current in a lateral direction parallel to an interfacing surface between two consecutive ILD layers of the N ILD layers. The electrically conductive line is present in at least two ILD layers of the N ILD layers. The electrically conductive line does not comprise an electrically conductive via that is adapted to carry a vertical electric current in a vertical direction perpendicular to the interfacing surface.Type: GrantFiled: October 17, 2007Date of Patent: March 8, 2011Assignee: International Business Machines CorporationInventors: Natalie Barbara Feilchenfeld, Zhong-Xiang He, Qizhi Liu, BethAnn Rainey, Ping-Chuan Wang, Kimball M. Watson
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Publication number: 20100210043Abstract: A system, method and device for measuring a depth of a Through-Silicon-Via (TSV) in a semiconductor device region on a wafer during in-line semiconductor fabrication, includes a resistance measurement trench structure having length and width dimensions in a substrate, ohmic contacts on a surface of the substrate disposed on opposite sides of the resistance measurement trench structure, and an unfilled TSV structure in semiconductor device region having an unknown depth. A testing circuit makes contact with the ohmic contacts and measures a resistance therebetween, and a processor connected to the testing circuit calculates a depth of the trench structure and the unfilled TSV structure based on the resistance measurement. The resistance measurement trench structure and the unfilled TSV are created simultaneously during fabrication.Type: ApplicationFiled: February 16, 2009Publication date: August 19, 2010Applicant: International Business Machines CorporationInventors: Qizhi Liu, Ping-Chuan Wang, Kimball M. Watson, Zhijian J. Yang
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Publication number: 20100032809Abstract: An array of through substrate vias (TSVs) is formed through a semiconductor substrate and a contact-via-level dielectric layer thereupon. A metal-wire-level dielectric layer and a line-level metal wiring structure embedded therein are formed directly on the contact-via-level dielectric layer. The line-level metal wiring structure includes cheesing holes that are filled with isolated portions of the metal-wire-level dielectric layer. In one embodiment, the entirety of the cheesing holes is located outside the area of the array of the TSVs to maximize the contact area between the TSVs and the line-level metal wiring structure. In another embodiment, a set of cheesing holes overlying an entirety of seams in the array of TSVs is formed to prevent trapping of any plating solution in the seams of the TSVs during plating to prevent corrosion of the TSVs at the seams.Type: ApplicationFiled: August 8, 2008Publication date: February 11, 2010Applicant: International Business Machines CorporationInventors: David S. Collins, Alvin Joseph, Peter J. Lindgren, Anthony K. Stamper, Kimball M. Watson
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Publication number: 20090273084Abstract: A structure and a method. The method includes: forming a dielectric layer on a substrate; forming electrically conductive first and second wires in the dielectric layer, top surfaces of the first and second wires coplanar with a top surface of the dielectric layer; and either (i) forming an electrically conductive third wire on the top surface of the dielectric layer, and over the top surfaces of the first and second wires, the third wire electrically contacting each of the first and second wires, the third wire not detectable by optical microscopy or (ii) forming an electrically conductive third wire between the top surface of the dielectric layer and the substrate, the third wire electrically contacting each of the first and second wires, the third wire not detectable by optical microscopy.Type: ApplicationFiled: May 5, 2008Publication date: November 5, 2009Inventors: Stephen Peter Ayotte, Jeffrey Peter Gambino, Timothy Dooling Sullivan, Kimball M. Watson
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Publication number: 20090253239Abstract: A method for fabricating a low-value resistor such as a ballast resistor for bipolar junction transistors. The resistor may be fabricated using layers of appropriate sheet resistance so as to achieve low resistance values in a compact layout. The method may rely on layers already provided by a conventional CMOS process flow, such as contact plugs and fully silicided (FUSI) metal gates.Type: ApplicationFiled: April 3, 2008Publication date: October 8, 2009Applicant: International Business Machines CorporationInventors: Douglas D. Coolbaugh, Ebenezer E. Eshun, Zhong-Xiang He, Robert M. Rassel, Kimball M. Watson
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Publication number: 20090152724Abstract: IC interconnect for high current device, design structure thereof and method are disclosed. One embodiment of the IC interconnect includes a first via positioned in a dielectric and coupled to a high current device at one end; a buffer metal segment positioned in a dielectric and coupled to the first via at the other end thereof; and a plurality of second vias positioned in a dielectric and coupled to the buffer metal segment at one end and to a metal power line at the other end thereof, wherein the buffer metal segment is substantially shorter in length than the metal power line.Type: ApplicationFiled: December 12, 2007Publication date: June 18, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ping-Chuan Wang, Kimball M. Watson, Kai Xiu
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Publication number: 20090140395Abstract: One or more multilayer back side metallurgy (BSM) stack structures are formed on thru-silicon-vias (TSV). The multiple layers of metal may include an adhesion layer of chromium on the semiconductor wafer back side, a conductive layer of copper, diffusion barrier layer of nickel and a layer of nobel metal, such as, gold. To prevent edge attack of copper after dicing, the layer of nickel is formed to seal the copper edge. To also prevent edge attack of the layer of nickel after dicing, the layer of gold is formed to seal both the layer of copper and the layer of nickel.Type: ApplicationFiled: December 4, 2007Publication date: June 4, 2009Applicant: International Business Machines CorporationInventors: Robert Edgar Davis, Robert Daniel Edwards, J. Edwin Hostetter, JR., Ping-Chuan Wang, Kimball M. Watson
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Publication number: 20090106726Abstract: A design structure including a semiconductor structure. The semiconductor structure includes (a) a substrate; (b) a first semiconductor device on the substrate; (c) N ILD (Inter-Level Dielectric) layers on the first semiconductor device, wherein N is an integer greater than one; and (d) an electrically conductive line electrically coupled to the first semiconductor device. The electrically conductive line is adapted to carry a lateral electric current in a lateral direction parallel to an interfacing surface between two consecutive ILD layers of the N ILD layers. The electrically conductive line is present in at least two ILD layers of the N ILD layers. The electrically conductive line does not comprise an electrically conductive via that is adapted to carry a vertical electric current in a vertical direction perpendicular to the interfacing surface.Type: ApplicationFiled: October 17, 2007Publication date: April 23, 2009Inventors: Natalie Barbara Feilchenfeld, Zhong-Xiang He, Qizhi Liu, BethAnn Rainey, Ping-Chuan Wang, Kimball M. Watson
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Publication number: 20080308940Abstract: A semiconductor structure. The semiconductor structure includes (a) a substrate; (b) a first semiconductor device on the substrate; (c) N ILD (Inter-Level Dielectric) layers on the first semiconductor device, wherein N is an integer greater than one; and (d) an electrically conductive line electrically coupled to the first semiconductor device. The electrically conductive line is adapted to carry a lateral electric current in a lateral direction parallel to an interfacing surface between two consecutive ILD layers of the N ILD layers. The electrically conductive line is present in at least two ILD layers of the N ILD layers. The electrically conductive line does not comprise an electrically conductive via that is adapted to carry a vertical electric current in a vertical direction perpendicular to the interfacing surface.Type: ApplicationFiled: August 26, 2008Publication date: December 18, 2008Inventors: Natalie Barbara Feilchenfeld, Zhong-Xiang He, Qizhi Liu, BethAnn Rainey, Ping-Chuan Wang, Kimball M. Watson
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Patent number: 7453151Abstract: A semiconductor structure and methods for forming the same. The semiconductor structure includes (a) a substrate; (b) a first semiconductor device on the substrate; (c) N ILD (Inter-Level Dielectric) layers on the first semiconductor device, wherein N is an integer greater than one; and (d) an electrically conductive line electrically coupled to the first semiconductor device. The electrically conductive line is adapted to carry a lateral electric current in a lateral direction parallel to an interfacing surface between two consecutive ILD layers of the N ILD layers. The electrically conductive line is present in at least two ILD layers of the N ILD layers. The electrically conductive line does not comprise an electrically conductive via that is adapted to carry a vertical electric current in a vertical direction perpendicular to the interfacing surface.Type: GrantFiled: July 27, 2006Date of Patent: November 18, 2008Assignee: International Business Machines CorporationInventors: Natalie Barbara Feilchenfeld, Zhong-Xiang He, Qizhi Liu, BethAnn Rainey, Ping-Chuan Wang, Kimball M. Watson
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Publication number: 20080194064Abstract: A method for programming a laser fuse. The laser fuse has a fuse link including a material having a characteristic of changing its electrical resistance after being exposed to a laser beam. The laser beam is directed to the fuse link, the laser beam being controlled such that, in response to the impact of the laser beam upon the fuse link, the electrical resistance of the fuse link changes but the fuse link is not blown off.Type: ApplicationFiled: April 18, 2008Publication date: August 14, 2008Inventors: Dinesh A. Badami, Tom C. Lee, Baozhen Li, Gerald Matusiewicz, William T. Motsiff, Christopher D. Muzzy, Kimball M. Watson, Jean E. Wynne
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Patent number: 7384824Abstract: A method and structure for fabricating a laser fuse and a method for programming the laser fuse. The laser fuse includes a dielectric layer having two vias filled with a first self-passivated electrically conducting material. A fuse link is on top of the dielectric layer. The fuse link electrically connects the two vias and includes a second material having a characteristic of changing its electrical resistance after being exposed to a laser beam. Two mesas are over the fuse link and directly over the two vias. The two mesas each include a third self-passivated electrically conducting material. The laser fuse is programmed by directing a laser beam to the fuse link. The laser beam is controlled such that, in response to the impact of the laser beam upon the fuse link, the electrical resistance of the fuse link changes but the fuse link is not blown off. Such electrical resistance change is sensed and converted to digital signal.Type: GrantFiled: February 27, 2006Date of Patent: June 10, 2008Assignee: International Business Machines CorporationInventors: Dinesh A. Badami, Tom C. Lee, Baozhen Li, Gerald Matusiewicz, William T. Motsiff, Christopher D. Muzzy, Kimball M. Watson, Jean E. Wynne
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Publication number: 20080122096Abstract: A semiconductor structure and methods for forming the same. The semiconductor structure includes (a) a substrate; (b) a first semiconductor device on the substrate; (c) N ILD (Inter-Level Dielectric) layers on the first semiconductor device, wherein N is an integer greater than one; and (d) an electrically conductive line electrically coupled to the first semiconductor device. The electrically conductive line is adapted to carry a lateral electric current in a lateral direction parallel to an interfacing surface between two consecutive ILD layers of the N ILD layers. The electrically conductive line is present in at least two ILD layers of the N ILD layers. The electrically conductive line does not comprise an electrically conductive via that is adapted to carry a vertical electric current in a vertical direction perpendicular to the interfacing surface.Type: ApplicationFiled: July 27, 2006Publication date: May 29, 2008Inventors: Natalie Barbara Feilchenfeld, Zhong-Xiang He, Qizhi Liu, BethAnn Rainey, Ping-Chuan Wang, Kimball M. Watson
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Publication number: 20080093659Abstract: Methods of electrically programming a diffusion resistor by using trapped charge in a trapped charge region adjacent to the resistor to vary the resistance of the resistor, and the resistor, are disclosed. In one embodiment, a method includes forming a diffusion resistor in a substrate; forming a trapped charge region adjacent to the diffusion resistor; and adjusting a resistance of the diffusion resistor by controlling the trapped charge in the trapped charge region.Type: ApplicationFiled: October 18, 2006Publication date: April 24, 2008Inventors: Benjamin T. Voegeli, Kimball M. Watson