Abstract: A method and structure for fabricating a laser fuse and a method for programming the laser fuse. The laser fuse includes a first dielectric layer having two vias filled with a first self-passivated electrically conducting material. A fuse link is on top of the first dielectric layer. The fuse link electrically connects the two vias and includes a second material having a characteristic of changing its electrical resistance after being exposed to a laser beam. Two mesas are over the fuse link and directly over the two vias. The two mesas each include a third self-passivated electrically conducting material. The laser fuse is programmed by directing a laser beam to the fuse link. The laser beam is controlled such that, in response to the impact of the laser beam upon the fuse link, the electrical resistance of the fuse link changes but the fuse link is not blown off. Such electrical resistance change is sensed and converted to digital signal.

Abstract: A multilayer semiconductor device that includes a metal-insulator-metal (MIM) capacitor including a first metal plate, a dielectric layer, and a second metal plate, a nitride etchstop layer formed above the MIM capacitor, a first interlayer dielectric formed on the nitride etchstop layer, and a first via and a second via that extend through at least the first interlayer dielectric to contact the nitride etchstop layer.

Abstract: A method and system are provided for determining a guard band voltage differential for testing a microprocessor. The guard band voltage differential approximates microprocessor circuit propagation delay degradation expected to occur over the life of the microprocessor. The system and method are performed by first partitioning a microprocessor into a plurality of cones of n circuit level models. Timing simulation data and degradation data are created to represent, respectively, the timing operation for each of the circuit level model circuit paths, and the hot-electron effects on propagation delay degradation for each of the circuit level models. Propagation delay is identified using this data for each of the circuit paths for the circuit level models at times corresponding to the beginning-of-life and end-of-life of the microprocessor. Propagation delay degradation is calculated as the difference between the propagation delay at these times.

Abstract: A method of assessing the tolerance of a microprocessor to propagation time degradation caused by electromigration effects and hot electron effects is provided. Reference values for interconnection resistance (IR) degradation and drain current (DC) degradation are compute, at nominal fabrication process and microprocessor lifetime application conditions. These results may be tabulated for a plurality of output driver load capacitances. Test IR degradation and test DC degradation values are calculated by scaling the reference IR and DC degradation values, respectively, for actual test conditions. The circuit propagation time and the propagation delay degradation caused by both electromigration and hot electron effects are calculated at process and lifetime environmental conditions.