Abstract: A manufacturing method includes forming one or more first holes in a cladding rod, inserting a first glass rod into each of the one or more first holes, heating the cladding rod together with the inserted first glass rod to integrate the first glass rod and the cladding rod and to form an intermediate preform, forming one or more second holes in the intermediate preform, inserting a second glass rod into each of the one or more second holes, and heating the intermediate preform together with the inserted second glass rod to integrate the second glass rod and the intermediate preform.

Abstract: An authentication terminal (2) includes a behavior information acquisition unit (232) that acquires a plurality of types of behavior information acquired on the basis of an action of a worker who is a subject of personal authentication, and an authentication unit (25) that performs identity authentication of the worker on the basis of a comprehensive evaluation obtained by comprehensively evaluating the plurality of types of the behavior information. The authentication terminal (2) performs the identity authentication of the worker on the basis of the comprehensive evaluation obtained by comprehensively evaluating the plurality of types of the behavior information, and thus can perform user-friendly personal authentication using the behavior information of an individual.

Abstract: A manufacturing method includes forming one or more first holes in a cladding rod, inserting a first glass rod into each of the one or more first holes, heating the cladding rod together with the inserted first glass rod to integrate the first glass rod and the cladding rod and to form an intermediate preform, forming one or more second holes in the intermediate preform, inserting a second glass rod into each of the one or more second holes, and heating the intermediate preform together with the inserted second glass rod to integrate the second glass rod and the intermediate preform.

Abstract: A measuring device that includes a base having a base reference surface to which a workpiece reference surface is opposed, measures a gap in an axial direction between the base reference surface and the workpiece reference surface by use of a fluid flowing between the base reference surface and the workpiece reference surface, in a state where the workpiece reference surface is opposed to the base reference surface. Dice, a distance to which in the axial direction from the base reference surface is known, form the external thread on the axial portion toward a direction away from the flange portion through rolling. A calculation device obtains a target position, in the axial direction, of the workpiece to be disposed on the dice, on the basis of the known distance and the measured gap.

Abstract: A measuring device that includes a base having a base reference surface to which a workpiece reference surface is opposed, measures a gap in an axial direction between the base reference surface and the workpiece reference surface by use of a fluid flowing between the base reference surface and the workpiece reference surface, in a state where the workpiece reference surface is opposed to the base reference surface. Dice, a distance to which in the axial direction from the base reference surface is known, form the external thread on the axial portion toward a direction away from the flange portion through rolling. A calculation device obtains a target position, in the axial direction, of the workpiece to be disposed on the dice, on the basis of the known distance and the measured gap.

Abstract: A program analysis support device that can freely combine program analysis conditions and can realize desired program analysis. An analysis condition setting part inputs a program analysis condition in a form of a conditional equation (analysis command, an analysis subject, and analysis condition) having an inherent equation number. A POU list extraction processing executing part executes an analysis command that reads a program to generate a collection of POUs serving as analysis subjects constituting the program, and a variable use list extraction processing executing part executes an analysis command that extracts a cross-reference of a variable to extract a cross-reference of a variable to the POU collection serving as the analysis subject. Both the parts further extract a cross-reference of a variable to another POU collection.

Abstract: A program analysis support device that can freely combine program analysis conditions and can realize desired program analysis. An analysis condition setting part inputs a program analysis condition in a form of a conditional equation (analysis command, an analysis subject, and analysis condition) having an inherent equation number. A POU list extraction processing executing part executes an analysis command that reads a program to generate a collection of POUs serving as analysis subjects constituting the program, and a variable use list extraction processing executing part executes an analysis command that extracts a cross-reference of a variable to extract a cross-reference of a variable to the POU collection serving as the analysis subject. Both the parts further extract a cross-reference of a variable to another POU collection.

Abstract: A liquid crystal composition for use in a DAP mode liquid crystal display device of a homeotropic structure type contains at least one kind of predetermined tolan derivative. The liquid crystal composition is used for a liquid crystal display device of an active-matrix drive type. The liquid crystal composition is also used for a projection type display. The content of the predetermined tolan derivative is in a range of 3 wt % to 20 wt %.

Abstract: A semiconductor integrated circuit device having a fuse-blown type ROM for storing information concerning defective bits for the replacement of defective bits in a semiconductor memory device, etc., with redundant bits. The integrated circuit device comprises fuses for constituting the ROM, pads for supplying a melting current to the fuses, and PN junctions each being formed, for example, by a semiconductor substrate and a diffusion layer formed on the semiconductor substrate. Each of the fuses is melted by applying voltage to a circuit connecting the PN junction, the fuse, and the pad so that the PN junction is forward biased, thereby supplying a large current to the fuse.

Abstract: In a semiconductor memory device, a decoder circuit is located between first and second memory cell arrays. A sequence of driver circuits in the decoder circuit is provided as driver circuits common to the first and second memory cell arrays. The output terminal of the driver circuit is connected directly with a data input/output portion for the first memory cell array and connected with another data input/output portion for the second memory cell array through wirings traversing the decoder circuit.

Abstract: A semiconductor memory device includes a write data transfer unit; a plurality of groups of sense amplifiers; a plurality of word lines; and a plurality of pairs of bit lines. Each of the pairs of bit lines includes a pair of inside bit lines, extending between the write data transfer unit and each of the sense amplifiers, and a pair of outside bit lines, extending from each of the sense amplifiers to the side opposite the side of the write data transfer unit. A plurality of memory cells is connected between the word lines and the pairs of bit lines, respectively. The drive timing of a selected one of the groups of sense amplifiers, connected to the selected one of pairs of bit lines on which the transfer of the write data is being performed, is delayed when compared with the drive timing of the sense amplifiers connected to the remaining pairs of bit lines on which the transfer of the write data is not being performed.

Abstract: A one-transistor one-capacitor type semiconductor memory device having a detection circuit for detecting the electric potential of a word line, to determine an appropriate timing for driving a sense amplifier, thereby improving the speed of memory operations.

Abstract: A semiconductor dynamic memory device having an improved refreshing time is disclosed wherein the memory device provides two buffer memories exclusively for the external and refresh addresses, each of the buffer memories comprising a preamplifier and a driver stage. When the falling edge of a RAS signal is detected, all the circuits are enabled in parallel, but the operation of the driver is suppressed. As soon as a CAS before RAS detector discriminates which of the falling edges of the CAS and RAS signals becomes low earlier, it sends an address driving signal to one of the drivers, and the external address or refresh address are sent immediately. Using this technique, the prior art sequential operation of discriminating the falling edges of RAS and CAS signal, sending the refresh signal, receiving it and switching the circuit from external address to refresh address is eliminated, and is replaced by a parallel operation. Thus the set up time of the dynamic memory is reduced to 1-2 n.sec.

Abstract: In a semiconductor integrated circuit having first and second power supply lines for receiving a power supply voltage, an external input terminal for receiving an input signal, and a high voltage detection circuit for detecting at the external input terminal a high voltage higher than a predetermined voltage which is higher than the power supply voltage, the high voltage detection circuit comprises an input circuit connected to the external input terminal for generating circuit for generating a reference voltage; and a differential voltage amplifier connected to receive the detection voltage and the reference voltage for amplifying the difference between the detection voltage and the reference voltage, to thereby determine whether the high voltage is applied, the input circuit comprising; a level shift element connected to the external input terminal for providing the detection voltage; an impedance element connected between the level shift element and the second power supply line; and a leak current compensa

Abstract: A semiconductor memory device including: a substrate; a plurality of word lines; a plurality of bit lines; and a plurality of memory cells, each positioned at an intersection defined by one of the word lines and one of the bit lines and including a transfer transistor and a capacitor. Each of the memory cells has a first insulating layer covering a gate of the transfer transistor. The capacitor in each memory cell includes a second conductive layer which contacts one of source and drain regions of the transfer transistor in the memory cell, through the first insulating layer, and extends over the gate of the transfer transistor, a second insulating layer formed on the first conductive layer, and a second conductive layer extending over the second insulating layer.

Abstract: A semiconductor integrated circuit including a memory unit for storing address information of a failed circuit portion and for replacing the failed circuit portion by a redundant circuit portion. The semiconductor integrated circuit provides a comparison unit for detecting coincidence between data read from the memory unit and a received input address. Data produced from the comparison by the comparison unit is delivered through an external connection terminal.

Abstract: A dynamic semiconductor memory device including memory cells divided into a plurality of blocks (1-1, 1-2). A simultaneous write enable circuit performs a write operation simultaneously upon the plurality of blocks, and a comparison circuit compares read data of one block with read data of the other block, thereby carrying out a test.

Abstract: In a semiconductor integrated circuit comprising an internal circuit, a device for receiving a chip select signal from the outside, a device for receiving an input signal from the outside, and a voltage detecting circuit for detecting whether or not the potential of the input signal is higher than a reference potential; the voltage detecting circuit comprises a first device for differentially comparing the potential of the input signal with the reference potential and generating an output potential in accordance with the results of the comparison, a second device for detecting a predetermined edge of the chip select signal so as to trigger the first device, and a third device for latching the output potential of the first device to the third device when the first device is triggered by the second device, the internal circuit being switched from a first mode to a second mode, or vice versa, in accordance with the output potential of the third device.

Abstract: A semiconductor memory device comprises a memory cell array, a bit line charge-up circuit coupled to one of a plurality of pairs of bit lines from the memory cell array for initially charging up the one pair of bit lines to a first voltage which is lower than a power source voltage used to drive the semiconductor memory device, an active restore circuit coupled to the one pair of bit lines and a switching circuit coupled to the one pair of bit lines for disconnecting the one pair of bit lines into a first pair of bit line sections on the side of the memory cell array and a second pair of bit line sections on the side of the active restore circuit after the one pair of bit lines are initially charged up to the first voltage. The active restore circuit charges up one of the pair of bit line sections on the side of the active restore circuit to a second voltage which is higher than the first voltage depending on a datum read out from the memory cell array.

Abstract: A semiconductor memory device capable of compensating for variation in a discriminating voltage of a memory cell comprising a memory cell and a gate circuit for coupling the memory cell to a bit line. The device has a precharge circuit for precharging the bit line pair to a predetermined resultant precharge voltage in a reset state. The precharge circuit precharges a bit line pair with the resultant precharge voltage obtained by adding a compensating voltage to a precharge voltage in the reset state. The compensating voltage is adapted to compensate for variation in a memory cell discriminating voltage based on variation in a memory cell voltage caused by capacitive coupling of a word line to a memory capacitor due to a parasitic capacitance of a gate circuit in the active state, and the precharge voltage is adapted to optimize the memory cell discriminating voltage when it is assumed that the parasitic capacitance is not present.