Abstract: A semiconductor memory device has an operational mode such as a nibble mode or page mode, a first address strobe signal is kept in an active state, and a second address strobe signal is successively switched between an active state and standby state, thereby enabling successive data output. Previous output data is reset once, in accordance with the switchover of the second address strobe signal to the active state while the first address strobe signal is in the active state, before outputting data, and the reset operation for outputting is also performed when both the first and second address strobe signals are switched to the standby state, so that the period in which the data is output is expanded.

Abstract: A booster circuit including a precharge capacitor (C.sub.2), a precharge driver circuit (20) having a first bootstrap circuit (C.sub.59, Q.sub.58, Q.sub.61) and precharging a voltage to the precharge capacitor in a reset mode, and an output driver circuit (19) having a switching circuit (Q.sub.21) for cutting off the output of the precharged voltage of the precharged capacitor in the reset mode and a second bootstrap circuit driving the switching circuit in an operation mode. The booster circuit further includes an additional switching circuit (Q.sub.1) for outputting a voltage to be superimposed onto the precharge voltage in the operation mode.The booster circuit may be applicable to a dynamic semiconductor memory device, for boosting a voltage of a word line at a high speed and for improving integration.

Abstract: In a semiconductor memory device including word lines (WL) and bit lines (BL), a regular pattern circuit area comprising elements regularly arranged in line with the word lines and/or the bit lines is divided into a plurality of blocks (1-1, 1-2). Provided between the divided blocks are irregular or peripheral circuit areas (2). Provided outside of the divided blocks are pads (P.sub.1 to P.sub.16).

Abstract: In a semiconductor memory device having stacked capacitor-type memory cells, the capacitor of each memory cell includes a base electrode, an insulating layer, and a counter electrode. The base electrode of each memory cell is partly superposed without contact on the base electrodes of other adjacent memory cells.

Abstract: In a semiconductor memory device having stacked capacitor-type memory cells, the capacitor of each memory cell comprises an electrode, an insulating layer, and a counter electrode. The electrode is connected electrically to a source or drain region of a transfer transistor and extends over a part of a word line adjacent to another word line serving a gate electrode of the transfer transistor, at which part no memory cell is formed.

Abstract: A semiconductor memory device including at least two groups, each of said groups including a plurality of memory cell array blocks. The number of the memory cell array blocks which are activated in one group is made different from the number of memory cell array blocks which are activated in another group by providing a sequential circuit, thus reducing the maximum power consumption.

Abstract: A semiconductor memory device comprises active pull-up circuits (APU.sub.1, APU.sub.2) each provided for one bit line (BL.sub.1, BL.sub.1). Each active pull-up circuit (APU.sub.1) has connections to two bit lines. That is, an active pull-up circuit (APU.sub.1) for a first bit line (BL.sub.1) comprises a first transistor (Q.sub.1) connected between a power supply terminal (V.sub.CC) and the first bit line, a second transistor (Q.sub.2) connected between the gate of the first transistor and the first bit line, and a capacitor (C.sub.1) connected to the gate of the first transistor. The gate of the second transistor is connected to a second bit line (BL.sub.1) which is paired with the first bit line. The capacitor receives an active pull-up signal (.phi..sub.AP). A circuit (Q.sub.3, Q.sub.4, Q.sub.5) is provided for transmitting a high level potential to the gate (N.sub.1) of the first transistor to precharge the capacitor.

Abstract: A dynamic semiconductor memory device comprising: (1) one-transistor one-capacitor type memory cells connected between word lines and bit lines and (2) flip-flops, each flip-flop being connected between a pair of word lines to clamp an unselected word line in the pair of word lines to the low voltage of a power source, thereby preventing a subsequent erroneous reading operation as a result of an increase in potential of the unselected word line.

Abstract: A semiconductor memory device having clamp circuits, each of which operates reliably without being affected by the resistance of a word line. Each of the clamp circuits is connected to a corresponding word line and clamps the potential of the word line to a reference potential when it is in a non-selected condition. Each of the clamp circuits includes a flip-flop having a first terminal connected to the corresponding word line and a second terminal which receives a control signal for operating each of the clamp circuits. The control signal is applied to the second terminal when the potential of a selected word line exceeds at least the potential necessary for inverting the condition of the flip-flop.

Abstract: A dynamic memory having single element storage cells. A plurality of gate circuits are connected to the column lines of the storage cell array at both ends of the column line. A plurality of sense amplifiers are disposed along both ends of the column lines and connected to the gate circuits. In accordance with switching of the gate circuits, a portion of the sense amplifiers are coupled with a portion of the column lines to perform a refresh operation and read or write operations for the storage cells connected thereto. Also, the remaining sense amplifiers are coupled with the remaining column lines to perform only the refresh operation of the storage cells connected to the remaining column lines.

Abstract: A dynamic semiconductor memory device includes a one-transistor one-capacitor type dynamic memory cell and a voltage dividing circuit having a potential providing terminal for providing an intermediate potential between the potential of the power supply and ground potential. One electrode of the capacitor in the memory cell is connected to the potential providing terminal. The voltage dividing circuit includes a potential switching circuit which changes the intermediate potential synchronously with an internal clock signal for selecting a word line, thus preventing a read error.