Patents by Inventor Kimihiko Kazui

Kimihiko Kazui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5737256
    Abstract: An 8-point inverse discrete cosine transform (IDCT) is decomposed into four 2-point IDCTs. The four 2-point IDCTs are implemented by four parallel-operating product-sum computing circuits. Each product-sum computing circuit comprises a single multiplying means and accomplishes computation of eight points in four clock cycles. Part of the multiplying means may be implemented by bit shift operation, and others by a semifixed multiplier. A two-dimensional 8.times.8 IDCT circuit is constructed which comprises three semifixed multipliers and one ordinary multiplier, and accomplishes IDCT computation of 8.times.8 points in 64 clock cycles.
    Type: Grant
    Filed: July 24, 1995
    Date of Patent: April 7, 1998
    Assignee: Fujitsu Limited
    Inventors: Akira Nakagawa, Kimihiko Kazui
  • Patent number: 5719963
    Abstract: A two-dimensional discrete cosine transform computing circuit has a transform block, formed by a multiplication unit and a Hadamard transform unit, which performs computations in a sequence of Hadamard transforms followed by multiplications in a two-dimensional discrete cosine transform, and in a sequence of multiplication followed by Hadamard transforms in an inverse two-dimensional discrete cosine transform. A memory block temporarily stores input/output data of the transform block; an input/output processing block performs pre-processing and post-processing such as cumulative addition and subtraction of input/output data of the transform block. A control block controls, when performing processing for either a two-dimensional discrete cosine transform or inverse two-dimensional discrete cosine transform, multiplications of coefficients in the transform block, read/write of the memory block, and the input/output processing block.
    Type: Grant
    Filed: May 31, 1995
    Date of Patent: February 17, 1998
    Assignee: Fujitsu Limited
    Inventors: Kimihiko Kazui, Kiyoshi Sakai, Kiichi Matsuda, Akira Nakagawa
  • Patent number: 5642174
    Abstract: A scene change detecting device of a relatively small circuit scale is capable of accurately detecting a scene change using data which have already been compressed and coded. The scene change detecting device has an extracting circuit for extracting frame type information, frame identification information, and block type information from a coded signal of a moving picture which has been processed by block-adaptive interframe predictive coding. The block type information is sent to a counter, and the frame type information and the frame identification information are sent to a frame estimating circuit. Based on the block type information, the counter counts macroblocks with respect to each of the types of predictive processes over one frame. The frame estimating circuit estimates a frame immediately following a scene change based on the counted number of macroblocks with respect to each of the types of predictive processes, the frame type information, and the frame identification information.
    Type: Grant
    Filed: August 21, 1996
    Date of Patent: June 24, 1997
    Assignee: Fujitsu Limited
    Inventors: Kimihiko Kazui, Eishi Morimatsu