Patents by Inventor Kimihiro Satoh

Kimihiro Satoh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10818731
    Abstract: The present invention is directed to a memory array including one or more memory layers, each of which includes a first plurality of memory cells and a second plurality of memory cells arranged in alternated odd and even columns, respectively; multiple odd horizontal lines with each connected to a respective odd column of the first plurality of memory cells; multiple even horizontal lines with each connected to a respective even column of the second plurality of memory cells; multiple transverse lines with each connected to one of the first plurality of memory cells and a respective one of the second plurality of memory cells disposed adjacent thereto along a row direction; and multiple vertical lines with each connected to a respective one of the multiple transverse lines. The odd horizontal lines collectively form fingers of a first comb structure and the even horizontal lines collectively form fingers of a second comb structure.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: October 27, 2020
    Assignee: Avalanche Technology, Inc.
    Inventor: Kimihiro Satoh
  • Patent number: 10522590
    Abstract: The present invention is directed to a memory device including a magnetic memory element; a horizontal conductive line disposed above the magnetic memory element; a bottom electrode formed beneath the magnetic memory element and having a top, first and second sides that are opposite to each other; a first vertical conductive line formed adjacent to the first side of the bottom electrode with a first volatile switching layer and a first electrode layer interposed therebetween; and a second vertical conductive line formed adjacent to the second side of the bottom electrode with a second volatile switching layer and a second electrode layer interposed therebetween. The magnetic memory element is electrically connected to the horizontal conductive line at one end and to the bottom electrode at the other end.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: December 31, 2019
    Assignee: Avalanche Technology, Inc.
    Inventors: Kimihiro Satoh, Hongxin Yang
  • Publication number: 20190288031
    Abstract: The present invention is directed to a memory device including a magnetic memory element; a horizontal conductive line disposed above the magnetic memory element; a bottom electrode formed beneath the magnetic memory element and having a top, first and second sides that are opposite to each other; a first vertical conductive line formed adjacent to the first side of the bottom electrode with a first volatile switching layer and a first electrode layer interposed therebetween; and a second vertical conductive line formed adjacent to the second side of the bottom electrode with a second volatile switching layer and a second electrode layer interposed therebetween. The magnetic memory element is electrically connected to the horizontal conductive line at one end and to the bottom electrode at the other end.
    Type: Application
    Filed: March 14, 2018
    Publication date: September 19, 2019
    Inventors: Kimihiro Satoh, Hongxin Yang
  • Patent number: 10224367
    Abstract: The present invention is directed to a memory device that includes an array of memory cells. Each of the memory cells includes a memory element connected to a two-terminal selector element. The two-terminal selector element includes a first electrode and a second electrode with a switching layer interposed therebetween. The switching layer includes a plurality of metal-rich clusters embedded in a nominally insulating matrix. One or more conductive paths are formed in the switching layer when an applied voltage to the memory cell exceeds a threshold level. Each of the memory cells may further include an intermediate electrode interposed between the memory element and the two-terminal selector element. The two-terminal selector element may further include a third electrode formed between the first electrode and the switching layer, and a fourth electrode formed between the second electrode and the switching layer.
    Type: Grant
    Filed: May 18, 2016
    Date of Patent: March 5, 2019
    Assignee: Avalanche Technology, Inc.
    Inventors: Hongxin Yang, Kimihiro Satoh, Xiaobin Wang
  • Patent number: 10153017
    Abstract: The present invention is directed to a method for sensing the resistance state of a memory cell that includes an MTJ memory element coupled to a two-terminal selector element in series. The method includes the steps of raising a cell voltage across the memory cell above a threshold voltage for the selector element to become conductive; decreasing the cell voltage to a first sensing voltage and measuring a first sensing current passing through the memory cell, the selector element being nominally conductive irrespective of the resistance state of the MTJ memory element at the first sensing voltage; and further decreasing the cell voltage to a second sensing voltage and measuring a second sensing current, the selector element being nominally conductive if the MTJ memory element is in the low resistance state or nominally insulative if the MTJ memory element is in the high resistance state at the second sensing voltage.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: December 11, 2018
    Assignee: Avalanche Technology, Inc.
    Inventors: Hongxin Yang, Xiaobin Wang, Jing Zhang, Xiaojie Hao, Zihui Wang, Kimihiro Satoh
  • Patent number: 10008540
    Abstract: The present invention is directed to a spin-orbitronics device including an array of MTJs with each of the MTJs coupled to a respective one of a plurality of selection transistors; a plurality of transverse polarizing lines with each of the transverse polarizing lines coupled to a row of the MTJs along a first direction; a plurality of word lines with each of the word lines coupled to gates of a row of the selection transistors along a second direction; and a plurality of source lines with each of the source lines coupled to a row of the selection transistors along a direction substantially perpendicular to the second direction. Each MTJ includes a magnetic comparison layer structure having a pseudo-invariable magnetization direction, which is configured to switch between two stable states by passing a comparison current through one of the plurality of transverse polarizing lines formed adjacent to the magnetic comparison layer structure.
    Type: Grant
    Filed: May 4, 2017
    Date of Patent: June 26, 2018
    Assignee: Avalanche Technology, Inc.
    Inventors: Parviz Keshtbod, Xiaobin Wang, Kimihiro Satoh, Zihui Wang, Huadong Gan
  • Publication number: 20180075891
    Abstract: The present invention is directed to a method for sensing the resistance state of a memory cell that includes an MTJ memory element coupled to a two-terminal selector element in series. The method includes the steps of raising a cell voltage across the memory cell above a threshold voltage for the selector element to become conductive; decreasing the cell voltage to a first sensing voltage and measuring a first sensing current passing through the memory cell, the selector element being nominally conductive irrespective of the resistance state of the MTJ memory element at the first sensing voltage; and further decreasing the cell voltage to a second sensing voltage and measuring a second sensing current, the selector element being nominally conductive if the MTJ memory element is in the low resistance state or nominally insulative if the MTJ memory element is in the high resistance state at the second sensing voltage.
    Type: Application
    Filed: September 14, 2016
    Publication date: March 15, 2018
    Inventors: Hongxin Yang, Xiaobin Wang, Jing Zhang, Xiaojie Hao, Zihui Wang, Kimihiro Satoh
  • Publication number: 20170338279
    Abstract: The present invention is directed to a memory device that includes an array of memory cells. Each of the memory cells includes a memory element connected to a two-terminal selector element. The two-terminal selector element includes a first electrode and a second electrode with a switching layer interposed therebetween. The switching layer includes a plurality of metal-rich clusters embedded in a nominally insulating matrix. One or more conductive paths are formed in the switching layer when an applied voltage to the memory cell exceeds a threshold level. Each of the memory cells may further include an intermediate electrode interposed between the memory element and the two-terminal selector element. The two-terminal selector element may further include a third electrode formed between the first electrode and the switching layer, and a fourth electrode formed between the second electrode and the switching layer.
    Type: Application
    Filed: May 18, 2016
    Publication date: November 23, 2017
    Inventors: Hongxin Yang, Kimihiro Satoh, Xiaobin Wang
  • Patent number: 9812499
    Abstract: The present invention is directed to a memory device including a memory cell coupled to two wiring lines at two ends thereof. The memory cell includes a memory element, which includes a magnetic free layer and a magnetic reference layer with a tunnel junction layer interposed therebetween, and a bi-directional two-terminal selector element having multiple threshold voltages coupled to the memory element in series. The magnetic free layer has a variable magnetization direction substantially perpendicular to a layer plane thereof and the magnetic reference layer has a fixed magnetization direction substantially perpendicular to a layer plane thereof. In an embodiment, the bi-directional two-terminal selector element includes two selector devices with each selector device including two electrodes with a switching layer interposed therebetween. In another embodiment, the bi-directional two-terminal selector element includes a selector device incorporating therein two switching layers.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: November 7, 2017
    Assignee: Avalanche Technology, Inc.
    Inventors: Kimihiro Satoh, Hongxin Yang
  • Patent number: 9793318
    Abstract: The present invention is directed to a memory device having a via landing pad in the peripheral circuit that minimizes the memory cell size. A device having features of the present invention comprises a peripheral circuit region and a magnetic memory cell region including at least a magnetic tunnel junction (MTJ) element. The peripheral circuit region comprises a substrate and a bottom contact formed therein; a landing pad including a first magnetic layer structure formed on top of the bottom contact and a second magnetic layer structure separated from the first magnetic layer structure by an insulating tunnel junction layer, wherein each of the insulating tunnel junction layer and the second magnetic layer structure has an opening aligned to each other; and a via partly embedded in the landing pad and directly coupled to the first magnetic layer structure through the openings.
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: October 17, 2017
    Assignee: Avalanche Technology, Inc.
    Inventors: Kimihiro Satoh, Yiming Huai
  • Publication number: 20170236868
    Abstract: The present invention is directed to a spin-orbitronics device including an array of MTJs with each of the MTJs coupled to a respective one of a plurality of selection transistors; a plurality of transverse polarizing lines with each of the transverse polarizing lines coupled to a row of the MTJs along a first direction; a plurality of word lines with each of the word lines coupled to gates of a row of the selection transistors along a second direction; and a plurality of source lines with each of the source lines coupled to a row of the selection transistors along a direction substantially perpendicular to the second direction. Each MTJ includes a magnetic comparison layer structure having a pseudo-invariable magnetization direction, which is configured to switch between two stable states by passing a comparison current through one of the plurality of transverse polarizing lines formed adjacent to the magnetic comparison layer structure.
    Type: Application
    Filed: May 4, 2017
    Publication date: August 17, 2017
    Inventors: Parviz Keshtbod, Xiaobin Wang, Kimihiro Satoh, Zihui Wang, Huadong Gan
  • Patent number: 9647032
    Abstract: The present invention is directed to a spin-orbitronics device including a magnetic comparison layer structure having a pseudo-invariable magnetization direction; a magnetic free layer structure whose variable magnetization direction can be switched by a switching current passing between the magnetic comparison layer structure and the magnetic free layer structure; an insulating tunnel junction layer interposed between the magnetic comparison layer structure and the magnetic free layer structure; and a non-magnetic transverse polarizing layer formed adjacent to the magnetic comparison layer structure. The pseudo-invariable magnetization direction of the magnetic comparison layer structure may be switched by passing a comparison current through the transverse polarizing layer along a direction that is substantially parallel to a layer plane of the transverse polarizing layer. The pseudo-invariable magnetization direction of the magnetic comparison layer structure is not switched by the switching current.
    Type: Grant
    Filed: August 20, 2015
    Date of Patent: May 9, 2017
    Assignee: Avalanche Technology, Inc.
    Inventors: Xiaobin Wang, Parviz Keshtbod, Kimihiro Satoh, Zihui Wang, Huadong Gan
  • Patent number: 9627438
    Abstract: The present invention is directed to a memory device including a first layer of memory cells with each cell of the first layer of memory cells including a two-terminal selection element coupled to a memory element in series; a plurality of first local wiring lines connected to one ends of the first layer of memory cells along a first direction with each of the first local wiring lines being electrically connected to two first line selection transistors at two ends thereof; and a plurality of second local wiring lines connected to other ends of the first layer of memory cells along a second direction substantially orthogonal to the first direction with each of the second local wiring lines being electrically connected to two second line selection transistors at two ends thereof.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: April 18, 2017
    Assignee: Avalanche Technology, Inc.
    Inventors: Kimihiro Satoh, Bing K. Yen
  • Patent number: 9548448
    Abstract: The present invention is directed to a semiconductor memory device including a plurality of first level contacts arranged in a rectangular array with parallel columns directed along a first direction and parallel rows directed along a second direction. The rectangular array of the plurality of first level contacts have a first pitch and a second pitch along the first and second directions, respectively. The memory device further includes a first and second plurality of second level contacts formed on top of the first level contacts with the first plurality of second level contacts electrically connected to odd columns along the second direction of the first level contacts and the second plurality of second level contacts electrically connected to even columns of the first level contacts; and a first and second plurality of memory elements formed on top of the first and second plurality of second level contacts, respectively.
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: January 17, 2017
    Assignee: Avalanche Technology, inc.
    Inventors: Kimihiro Satoh, Bing K. Yen, Dong Ha Jung, Yiming Huai
  • Publication number: 20160276406
    Abstract: The present invention is directed to a memory device having a via landing pad in the peripheral circuit that minimizes the memory cell size. A device having features of the present invention comprises a peripheral circuit region and a magnetic memory cell region including at least a magnetic tunnel junction (MTJ) element. The peripheral circuit region comprises a substrate and a bottom contact formed therein; a landing pad including a first magnetic layer structure formed on top of the bottom contact and a second magnetic layer structure separated from the first magnetic layer structure by an insulating tunnel junction layer, wherein each of the insulating tunnel junction layer and the second magnetic layer structure has an opening aligned to each other; and a via partly embedded in the landing pad and directly coupled to the first magnetic layer structure through the openings.
    Type: Application
    Filed: May 19, 2016
    Publication date: September 22, 2016
    Inventors: Kimihiro Satoh, Yiming Huai
  • Patent number: 9373663
    Abstract: The present invention is directed to a memory device having a via landing pad in the peripheral circuit that minimizes the memory cell size. A device having features of the present invention comprises a peripheral circuit region and a magnetic memory cell region including at least a magnetic tunnel junction (MTJ) element. The peripheral circuit region comprises a substrate and a bottom contact formed therein; a landing pad including a first magnetic layer structure formed on top of the bottom contact and a second magnetic layer structure separated from the first magnetic layer structure by an insulating tunnel junction layer, wherein each of the insulating tunnel junction layer and the second magnetic layer structure has an opening aligned to each other; and a via partly embedded in the landing pad and directly coupled to the first magnetic layer structure through the openings.
    Type: Grant
    Filed: September 20, 2013
    Date of Patent: June 21, 2016
    Assignee: Avalanche Technology, Inc.
    Inventors: Kimihiro Satoh, Yiming Huai
  • Publication number: 20160064650
    Abstract: The present invention is directed to a spin-orbitronics device including a magnetic comparison layer structure having a pseudo-invariable magnetization direction; a magnetic free layer structure whose variable magnetization direction can be switched by a switching current passing between the magnetic comparison layer structure and the magnetic free layer structure; an insulating tunnel junction layer interposed between the magnetic comparison layer structure and the magnetic free layer structure; and a non-magnetic transverse polarizing layer formed adjacent to the magnetic comparison layer structure. The pseudo-invariable magnetization direction of the magnetic comparison layer structure may be switched by passing a comparison current through the transverse polarizing layer along a direction that is substantially parallel to a layer plane of the transverse polarizing layer. The pseudo-invariable magnetization direction of the magnetic comparison layer structure is not switched by the switching current.
    Type: Application
    Filed: August 20, 2015
    Publication date: March 3, 2016
    Inventors: Xiaobin Wang, Parviz Keshtbod, Kimihiro Satoh, Zihui Wang, Huadong Gan
  • Patent number: 9209390
    Abstract: A memory device comprises a semiconductor substrate having a plurality of parallel trenches therein, a memory region formed in the substrate including an array of memory cells having a plurality of vertical selection transistors with respective channels formed in trench sidewalls, a plurality of buried source electrodes in trench bottoms, a plurality of paired gate electrodes formed on paired trench sidewalls, a first and second stitch region disposed adjacent the memory region along a trench direction including a first and second row of gate contacts, respectively, and a row of source contacts disposed in the first or second stitch region with each of the source contacts coupled to a respective one of the source electrodes. One of each pair of the gate electrodes is coupled to a respective one of the first row of gate contacts and the other one of each pair of gate electrodes is coupled to a respective one of the second row of gate contacts.
    Type: Grant
    Filed: April 13, 2015
    Date of Patent: December 8, 2015
    Assignee: Avalanche Technology, Inc.
    Inventors: Kimihiro Satoh, Jing Zhang, Yiming Huai
  • Patent number: 9166154
    Abstract: Fabrication methods using Ion Beam Etching (IBE) for MRAM cell memory elements are described. In embodiments of the invention the top electrode and MTJ main body are etched with one mask using reactive etching such as RIE or magnetized inductively coupled plasma (MICP) for improved selectivity, then the bottom electrode is etched using IBE as specified in various alternative embodiments which include selection of incident angles, wafer rotational rate profiles and optional passivation layer deposited prior to the IBE. The IBE according to the invention etches the bottom electrode without the need for an additional mask by using the layer stack created by the first etching phase as the mask. This makes the bottom electrode self-aligned to MTJ. The IBE also achieves MTJ sidewall cleaning without the need for an additional step.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: October 20, 2015
    Assignee: Avalance Technology, Inc.
    Inventors: Kimihiro Satoh, Dong Ha Jung, Jing Zhang, Benjamin Chen, Yiming Huai, Rajiv Yadav Ranjan, Yuchen Zhou
  • Patent number: 9123575
    Abstract: The present invention is directed to a semiconductor memory device including a plurality of first level contacts arranged in an array with every third row vacant along a first direction, thereby forming multiple contact regions separated by multiple vacant regions along the first direction with each of the multiple contact regions including a first row and a second row of the first level contacts extending along a second direction; a first and second plurality of second level contacts formed on top of the first level contacts with the second plurality of second level contacts having elongated shape extending into the vacant regions adjacent thereto; and a first and second plurality of memory elements formed on top of the first and second plurality of second level contacts, respectively, thereby permitting the memory elements to have greater center-to-center distance between two closest neighbors than the first level contacts.
    Type: Grant
    Filed: July 21, 2014
    Date of Patent: September 1, 2015
    Assignee: Avalanche Technology, Inc.
    Inventors: Kimihiro Satoh, Bing K Yen, Dong Ha Jung, Yiming Huai