Abstract: Row electrodes X, Y have bus electrodes Xb, Yb extending in the row direction and a plurality of transparent electrodes Xa, Xa′, Ya, Ya′ extending in the column direction, arranged along the bus electrodes Xb, Yb and connected to the bus electrodes Xb, Yb with intersecting. Each end of the transparent electrodes Xa, Xa′, Ya, Ya′ of one of the row electrodes X, Y and each end of the corresponding transparent electrodes Xa, Xa′, Ya, Ya′ of the other are opposed to each other with a discharge gap g in between. Discharge cells C, C′ are formed in a discharge space between a front glass substrate 10 and a back glass substrate 13, opposing the transparent electrodes Xa, Xa′, Ya, Ya′, which form pairs by opposing each other.

Abstract: A plasma display panel is provided with discharge cells CB, CG, CR at intersecting positions of row electrode pairs (X, Y) formed on a front glass substrate 10 and column electrodes D formed on a back glass substrate 13, and formed with phosphor layers 16B, 16G, 16R of the three primary colors of red, green and blue in the discharge cells CB, CG, CR in order. In such plasma display panel, the discharge cell CR formed with a red phosphor layer 16R, the discharge cell CG formed with a green phosphor layer 16G and the discharge cell CB formed with a blue phosphor layer 16B respectively have opening areas SB, SG, SR opening toward the front glass substrate 10, which are set to be increased with decreasing order of luminance in accordance with each luminance of red, green and blue colors.

Abstract: Each of partition walls 25 comprises vertical walls 25a each positioned between adjacent discharge cells C1 in the row direction and extending in the column direction to form a partition between the adjacent discharge cells C1, and transverse walls 25b bridging the vertical walls 25a to define a top and bottom edge of the discharge cells C1. Each of the transverse walls 25b of the partition wall 25 is provided in a shape that its central part j1 located midway between adjacent vertical walls 25a protrudes beyond its part j2 coupled to the vertical wall 25a toward the outside of the discharge cell C1 in the column direction.

Abstract: An additional dielectric layer (11A) is formed on a backside of a dielectric layer (11) to protrude to the inside of a discharge space (S) and extend along an edge of a discharge cell C in parallel to the row direction. Row electrodes (X, Y) respectively have bus electrodes (Xb, Yb) extending along the edge of the discharge cells (C) in the row direction, and transparent electrodes (Xa, Ya) paired with each other in each discharge cell C. An overlap portion (m) of a proximal end (Xa3, Ya3) of each transparent electrode (Xa, Ya) connected to the bus electrode (Xb, Yb), which overlaps the additional dielectric layer (11A), is designed to be smaller in width than that of a linking portion (Xa2, Ya2) between the overlapping portion (m) and a distal end of the transparent electrode.

Abstract: In a plasma display panel, a floating electrode (F1) is provided each portion on at least one of the front glass substrate (10) and the back glass substrate (13) facing the vertical wall (15a) of the partition wall (15) defining partition between the discharge cells (C) adjacent to each other in the row direction, and formed with the same materials as the transparent electrode (Xa, Ya) or the bus electrode (Xb, Yb).

Abstract: A plasma display panel has a pair of substrates, a pair of opposed row electrodes disposed adjacently to the display side substrate interposed by a discharge gap, and a dielectric layer covering the row electrodes. The dielectric layer is formed except in the discharge space, thereby forming a vacant space or groove in the discharge gap.

Abstract: A plasma display panel comprises a front substrate and a rear substrate, a plurality of row electrode pairs provided on the inner surface of the front substrate, a dielectric layer provided on the inner surface of the front substrate for coverring the row electrode pairs, a plurality of column electrodes provided on the inner surface of the rear substrate, a partition wall assembly provided between the front substrate and the rear substrate, said partition wall assembly including a plurality of longitudinal partition walls and a plurality of lateral partition walls, forming a plurality of discharge cells. In particular, the dielectric layer has a plurality of projection portions located corresponding to and protruding toward the lateral partition walls of the partition wall assembly, in a manner such that there would be no slots formed between the dielectric layer and the lateral partition walls.

Abstract: An object of the present invention is to provide a high definition PDP screen without lowering the PDP luminescence efficiency.

Abstract: A plasma display panel comprises a plurality of row electrode pairs (X, Y) provided on a front glass substrate 10, a plurality of column electrodes D provided on a back glass substrate 13 and each intersecting the row electrode pairs, and discharge cells C which are defined in a discharge space S to correspond to the respective intersections. The row electrode Y of each row electrode pair (X, Y) has transparent electrodes Ya each constructed by a leading member Ya1 and a base member Ya2. The column electrode D is provided with enlargement members Da, having a width in a row direction larger than that of the base member Ya2, in a position opposite to the leading member Ya1.

Abstract: A plasma display panel including a partition wall (35) arranged between a front substrate (10) and a back substrate (13), and having vertical walls (35a) extending in the column direction and transverse walls (35b) extending in the row direction to define a discharge space (S) into each discharge cell (C) in the row direction and the column direction. A clearance (SL) extending in parallel to the row direction divides the transverse wall (35b) situated between the adjacent discharge cells (c) respectively in the column direction to each other. A groove (11Aa) formed in the additional dielectric layer (11A) makes communication between the inside of the clearance (SL) and the inside of the adjacent discharge cells (C) in the column direction.

Abstract: An object of the present invention is to provide a plasma display device that enables high-luminosity display while keeping consumption of power low. After causing reset discharge to form a wall charge in the dielectric layer of all discharge cells of a plasma display panel, pixel data are written by causing selective erasure discharge to erase, in accordance to pixel data corresponding to an input video signal, the wall charge formed in each discharge cell, and sustaining pulses, with a voltage value of at least 200 volts, are applied alternately to each row electrode of each row electrode pair of the plasma display panel to repeatedly cause sustained discharge to occur only in discharge cells having residual wall charge.

Abstract: A plasma display panel includes a front substrate and a rear substrate, a plurality of row electrode pairs provided on the inner surface of the front substrate, a dielectric layer provided on the inner surface of the front substrate for coverring the row electrode pairs, a plurality of column electrodes provided on the inner surface of the rear substrate, a partition wall assembly provided between the front substrate and the rear substrate, said partition wall assembly including a plurality of longitudinal partition walls and a plurality of lateral partition walls, forming a plurality of discharge cells. In particular, the dielectric layer has a plurality of projection portions located corresponding to and protruding toward the lateral partition walls of the partition wall assembly, in a manner such that there would be no slots formed between the dielectric layer and the lateral partition walls.

Abstract: A plasma display panel comprises a front substrate and a rear substrate, a plurality of row electrode pairs provided on the inner surface of the front substrate, a dielectric layer provided on the inner surface of the front substrate for coverring the row electrode pairs, a plurality of column electrodes provided on the inner surface of the rear substrate, a partition wall assembly provided between the front substrate and the rear substrate, said partition wall assembly including a plurality of longitudinal partition walls and a plurality of lateral partition walls, forming a plurality of discharge cells. In particular, the dielectric layer has a plurality of projection portions located corresponding to and protruding toward the lateral partition walls of the partition wall assembly, in a manner such that there would be no slots formed between the dielectric layer and the lateral partition walls.

Abstract: A plasma display panel comprises a front substrate and a rear substrate, a plurality of row electrode pairs provided on the inner surface of the front substrate, a dielectric layer provided on the inner surface of the front substrate for coverring the row electrode pairs, a plurality of column electrodes provided on the inner surface of the rear substrate, a partition wall assembly provided between the front substrate and the rear substrate, said partition wall assembly including a plurality of longitudinal partition walls and a plurality of lateral partition walls, forming a plurality of discharge cells. In particular, the dielectric layer has a plurality of projection portions located corresponding to and protruding toward the lateral partition walls of the partition wall assembly, in a manner such that there would be no slots formed between the dielectric layer and the lateral partition walls.

Abstract: A plasma display panel comprises a front substrate and a rear substrate, a plurality of row electrode pairs provided on the inner surface of the front substrate, a dielectric layer provided on the inner surface of the front substrate for coverring the row electrode pairs, a plurality of column electrodes provided on the inner surface of the rear substrate, a partition wall assembly provided between the front substrate and the rear substrate, said partition wall assembly including a plurality of longitudinal partition walls and a plurality of lateral partition walls, forming a plurality of discharge cells. In particular, the dielectric layer has a plurality of projection portions located corresponding to and protruding toward the lateral partition walls of the partition wall assembly, in a manner such that there would be no slots formed between the dielectric layer and the lateral partition walls.

Abstract: A plasma display panel includes a front glass substrate 1 having the back surface on which a plurality of pairs of row electrodes X1, Y1 are formed, a back glass substrate 4 on which column electrodes D are formed, and partition walls 6 made of dielectric materials and defining individual discharge cells C, in which at least either of the row electrodes X1 and Y1 is placed at a position shifted relatively in the column direction toward decreasing the overlapping of the row electrode and the partition wall in reference to the partition wall 6.

Abstract: An object of the present invention is to provide a plasma display device that enables high-luminosity display while keeping consumption of power low. After causing reset discharge to form a wall charge in the dielectric layer of all discharge cells of a plasma display panel, pixel data are written by causing selective erasure discharge to erase, in accordance to pixel data corresponding to an input video signal, the wall charge formed in each discharge cell, and sustaining pulses, with a voltage value of at least 200 volts, are applied alternately to each row electrode of each row electrode pair of the plasma display panel to repeatedly cause sustained discharge to occur only in discharge cells having residual wall charge.

Abstract: A plasma display panel has, on the display-side inner surface of one substrate out of a pair of substrates disposed opposite to each other via a discharge space, plural pairs of row electrodes extending in parallel in a first direction with each discharge gap held therebetween, dielectric layers for the row electrodes with respect to the discharge space; and on the back-side inner surface of the other substrate disposed opposite to the display-side substrate, plural pairs of column electrodes extending in a second direction perpendicularly crossing the first direction and forming unit luminous areas in intersecting portions with respect to the respective pairs of row electrodes, and belt-like partition walls for partitioning the discharge space into the unit luminous areas in the first direction.

Abstract: An object of the present invention is to provide a plasma display device that enables high-luminosity display while keeping consumption of power low. After causing reset discharge to form a wall charge in the dielectric layer of all discharge cells of a plasma display panel, pixel data are written by causing selective erasure discharge to erase, in accordance to pixel data corresponding to an input video signal, the wall charge formed in each discharge cell, and sustaining pulses, with a voltage value of at least 200 volts, are applied alternately to each row electrode of each row electrode pair of the plasma display panel to repeatedly cause sustained discharge to occur only in discharge cells having residual wall charge.

Abstract: A plasma display panel has a plurality of first and second sustain electrodes, a plurality of address electrodes which intersect with the sustain electrodes to form a pixel at every intersection. In the method, an address period is provided, in which data pulses are applied to the address electrodes, and scanning pulses are applied to the second sustain electrodes, thereby selecting lighted pixels and unlighted pixels. A discharge sustaining period is provided, in which discharge sustaining pulses are alternately applied to the first and second sustain electrodes so as to sustain the lighted and unlighted pixels. An offset voltage having the same polarity as the data pulse is applied to the address electrodes in the discharge sustaining period.