Patents by Inventor Kin F. Ma
Kin F. Ma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6888762Abstract: A DRAM memory array is disclosed that uses a current limiting circuit employing current feedback to clamp the current flow to reduced levels than were previously possible. The current limiting circuit comprises a long length, depletion mode transistor that has its gate voltage reduced when row-to-column shorts exist to limit the bleed current. An alternative embodiment uses a P-channel FET in series with the depletion mode transistor and has its gate tied to a negative supply and passes current until both digit lines approach approximately 0.3 Volts.Type: GrantFiled: August 11, 2003Date of Patent: May 3, 2005Assignee: Micron Technology, Inc.Inventors: Manny Kin F. Ma, Brian Shirley
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Patent number: 6724033Abstract: A masking and etching technique during the formation of a memory cell capacitor which simultaneously separates storage poly into individual storage poly nodes and etches recesses into the storage poly nodes which increase the surface area of the storage poly nodes and thereby increase the capacitance of a completed memory cell without additional processing steps.Type: GrantFiled: January 20, 1999Date of Patent: April 20, 2004Inventors: Aaron Schoenfeld, Manny Kin F. Ma
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Patent number: 6707096Abstract: A masking and etching technique during the formation of a memory cell capacitor which simultaneously separates storage poly into individual storage poly nodes and etches recesses into the storage poly nodes which increase the surface area of the storage poly nodes and thereby increase the capacitance of a completed memory cell without additional processing steps.Type: GrantFiled: January 3, 2002Date of Patent: March 16, 2004Assignee: Micron Technology, Inc.Inventors: Aaron Schoenfeld, Manny Kin F. Ma
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Publication number: 20040032784Abstract: A DRAM memory array is disclosed that uses a current limiting circuit employing current feedback to clamp the current flow to reduced levels than were previously possible. The current limiting circuit comprises a long length, depletion mode transistor that has its gate voltage reduced when row-to-column shorts exist to limit the bleed current. An alternative embodiment uses a P-channel FET in series with the depletion mode transistor and has its gate tied to a negative supply and passes current until both digit lines approach approximately 0.3 Volts.Type: ApplicationFiled: August 11, 2003Publication date: February 19, 2004Inventors: Manny Kin F. Ma, Brian Shirley
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Patent number: 6682954Abstract: A method for upgrading or remediating semiconductor devices utilizing a remediation, adaptation, modification or upgrade chip in a piggyback configuration with a primary bare chip to achieve an upgrade, modification or adaptation of the primary chip or remedy a design or fabrication problem with the primary chip.Type: GrantFiled: January 31, 1997Date of Patent: January 27, 2004Assignee: Micron Technology, Inc.Inventors: Manny Kin F. Ma, Jeffrey D. Bruce
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Patent number: 6631091Abstract: A DRAM memory array is disclosed that uses a current limiting circuit employing current feedback to clamp the current flow to reduced levels than were previously possible. The current limiting circuit comprises a long length, depletion mode transistor that has its gate voltage reduced when row-to-column shorts exist to limit the bleed current. An alternative embodiment uses a P-channel FET in series with the depletion mode transistor and has its gate tied to a negative supply and passes current until both digit lines approach approximately 0.3 Volts.Type: GrantFiled: July 22, 2002Date of Patent: October 7, 2003Assignee: Micron Technology, Inc.Inventors: Manny Kin F. Ma, Brian Shirley
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Patent number: 6625068Abstract: A DRAM memory array is disclosed that uses a current limiting circuit employing current feedback to clamp the current flow to reduced levels than were previously possible. The current limiting circuit comprises a long length, depletion mode transistor that has its gate voltage reduced when row-to-column shorts exist to limit the bleed current. An alternative embodiment uses a P-channel FET in series with the depletion mode transistor and has its gate tied to a negative supply and passes current until both digit lines approach approximately 0.3 Volts.Type: GrantFiled: July 25, 2002Date of Patent: September 23, 2003Assignee: Micron Technology, Inc.Inventors: Manny Kin F. Ma, Brian Shirley
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Patent number: 6599840Abstract: Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the material on a semiconductor substrate. The material, which has uniform stress therein, is then masked, and the stress in a portion of the material is reduced, such as by implanting ions into an unmasked portion. The mask is removed, and either the high stress masked portion or the low stress unmasked portion of the material is selectively removed, preferably by an etching process. The portion of the material not removed remains and forms a shaped structure. The various methods are used to form raised shaped structures, shaped openings, polysilicon plugs, capacitor storage nodes, surround-gate transistors, free-standing walls, interconnect lines, trench capacitors, and trench isolation regions.Type: GrantFiled: July 11, 2002Date of Patent: July 29, 2003Assignee: Micron Technology, Inc.Inventors: Zhiqiang Wu, Li Li, Thomas A. Figura, Kunal R. Parekh, Pai-Hung Pan, Alan R. Reinberg, Kin F. Ma
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Patent number: 6596648Abstract: Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the material on a semiconductor substrate. The material, which has uniform stress therein, is then masked, and the stress in a portion of the material is reduced, such as by implanting ions into an unmasked portion. The mask is removed, and either the high stress masked portion or the low stress unmasked portion of the material is selectively removed, preferably by an etching process. The portion of the material not removed remains and forms a shaped structure. The various methods are used to form raised shaped structures, shaped openings, polysilicon plugs, capacitor storage nodes, surround-gate transistors, free-standing walls, interconnect lines, trench capacitors, and trench isolation regions.Type: GrantFiled: July 11, 2002Date of Patent: July 22, 2003Assignee: Micron Technology, Inc.Inventors: Zhiqiang Wu, Li Li, Thomas A. Figura, Kunal R. Parekh, Pai-Hung Pan, Alan R. Reinberg, Kin F. Ma
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Patent number: 6596642Abstract: Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the material on a semiconductor substrate. The material, which has uniform stress therein, is then masked, and the stress in a portion of the material is reduced, such as by implanting ions into an unmasked portion. The mask is removed, and either the high stress masked portion or the low stress unmasked portion of the material is selectively removed, preferably by an etching process. The portion of the material not removed remains and forms a shaped structure. The various methods are used to form raised shaped structures, shaped openings, polysilicon plugs, capacitor storage nodes, surround-gate transistors, free-standing walls, interconnect lines, trench capacitors, and trench isolation regions.Type: GrantFiled: July 11, 2002Date of Patent: July 22, 2003Assignee: Micron Technology, Inc.Inventors: Zhiqiang Wu, Li Li, Thomas A. Figura, Kunal R. Parekh, Pai-Hung Pan, Alan R. Reinberg, Kin F. Ma
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Patent number: 6593764Abstract: A test socket for testing a packaged semiconductor device. The test socket includes a test substrate, at least one support member, and at least one securing member. Terminals of the test substrate are electrically connectable to a testing device. The terminals may by located within recesses that are configured to receive leads. The shapes of each support member and securing member may be complementary to the respective shapes of the bottom and top surfaces of leads extending from the packaged semiconductor device. Upon placement of a packaged semiconductor device on the test substrate, the leads are aligned with and positioned against their corresponding terminals and the support member. The securing elements are then placed against the leads to bias each lead against its corresponding terminal.Type: GrantFiled: October 29, 2002Date of Patent: July 15, 2003Assignee: Micron Technology, Inc.Inventors: Chris G. Martin, Manny Kin F. Ma
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Patent number: 6570258Abstract: An embodiment of the present invention discloses a memory device having an array with digit lines arranged in complementary pairs, the array comprising; a substantially planar layer having trenches therein; a first level of digit lines residing at least partially in the trenches; a second level of digit lines residing on the surface of the layer, the second level extending in generally parallel relation to the digit lines in the first level. The first level of digit lines are in alternating positions with the second level of digit lines and the alternating positions comprise a repeating pattern of a first complementary pair of digit lines at the first level adjacent a second complementary pair of digit lines at the second level.Type: GrantFiled: June 18, 2001Date of Patent: May 27, 2003Assignee: Micron Technology, Inc.Inventors: Kin F. Ma, Eric T. Stubbs
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Publication number: 20030057985Abstract: A test socket for testing a packaged semiconductor device. The test socket includes a test substrate, at least one support member, and at least one securing member. Terminals of the test substrate are electrically connectable to a testing device. The terminals may by located within recesses that are configured to receive leads. The shapes of each support member and securing member may be complementary to the respective shapes of the bottom and top surfaces of leads extending from the packaged semiconductor device. Upon placement of a packaged semiconductor device on the test substrate, the leads are aligned with and positioned against their corresponding terminals and the support member. The securing elements are then placed against the leads to bias each lead against its corresponding terminal.Type: ApplicationFiled: October 29, 2002Publication date: March 27, 2003Inventors: Chris G. Martin, Manny Kin F. Ma
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Publication number: 20020187648Abstract: Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the material on a semiconductor substrate. The material, which has uniform stress therein, is then masked, and the stress in a portion of the material is reduced, such as by implanting ions into an unmasked portion. The mask is removed, and either the high stress masked portion or the low stress unmasked portion of the material is selectively removed, preferably by an etching process. The portion of the material not removed remains and forms a shaped structure. The various methods are used to form raised shaped structures, shaped openings, polysilicon plugs, capacitor storage nodes, surround-gate transistors, free-standing walls, interconnect lines, trench capacitors, and trench isolation regions.Type: ApplicationFiled: July 11, 2002Publication date: December 12, 2002Inventors: Zhiqiang Wu, Li Li, Thomas A. Figura, Kunal R. Parekh, Pai-Hung Pan, Alan R. Reinberg, Kin F. Ma
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Publication number: 20020182872Abstract: Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the material on a semiconductor substrate. The material, which has uniform stress therein, is then masked, and the stress in a portion of the material is reduced, such as by implanting ions into an unmasked portion. The mask is removed, and either the high stress masked portion or the low stress unmasked portion of the material is selectively removed, preferably by an etching process. The portion of the material not removed remains and forms a shaped structure. The various methods are used to form raised shaped structures, shaped openings, polysilicon plugs, capacitor storage nodes, surround-gate transistors, free-standing walls, interconnect lines, trench capacitors, and trench isolation regions.Type: ApplicationFiled: July 11, 2002Publication date: December 5, 2002Inventors: Zhiqiang Wu, Li Li, Thomas A. Figura, Kunal R. Parekh, Pai-Hung Pan, Alan R. Reinberg, Kin F. Ma
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Publication number: 20020182816Abstract: Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the material on a semiconductor substrate. The material, which has uniform stress therein, is then masked, and the stress in a portion of the material is reduced, such as by implanting ions into an unmasked portion. The mask is removed, and either the high stress masked portion or the low stress unmasked portion of the material is selectively removed, preferably by an etching process. The portion of the material not removed remains and forms a shaped structure. The various methods are used to form raised shaped structures, shaped openings, polysilicon plugs, capacitor storage nodes, surround-gate transistors, free-standing walls, interconnect lines, trench capacitors, and trench isolation regions.Type: ApplicationFiled: July 11, 2002Publication date: December 5, 2002Inventors: Zhiqiang Wu, Li Li, Thomas A. Figura, Kunal R. Parekh, Pai-Hung Pan, Alan R. Reinberg, Kin F. Ma
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Publication number: 20020181300Abstract: A DRAM memory array is disclosed that uses a current limiting circuit employing current feedback to clamp the current flow to reduced levels than were previously possible. The current limiting circuit comprises a long length, depletion mode transistor that has its gate voltage reduced when row-to-column shorts exist to limit the bleed current. An alternative embodiment uses a P-channel FET in series with the depletion mode transistor and has its gate tied to a negative supply and passes current until both digit lines approach approximately 0.3 Volts.Type: ApplicationFiled: July 22, 2002Publication date: December 5, 2002Inventors: Manny Kin F. Ma, Brian Shirley
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Patent number: 6472893Abstract: A test socket for testing a packaged semiconductor device. The test socket includes a test substrate, at least one support member, and at least one securing member. Terminals of the test substrate are electrically connectable to a testing device. The terminals may by located within recesses that are configured to receive leads. The shapes of each support member and securing member may be complementary to the respective shapes of the bottom and top surfaces of leads extending from the packaged semiconductor device. Upon placement of a packaged semiconductor device on the test substrate, the leads are aligned with and positioned against their corresponding terminals and the support member. The securing elements are then placed against the leads to bias each lead against its corresponding terminal.Type: GrantFiled: December 28, 2001Date of Patent: October 29, 2002Assignee: Micron Technology, Inc.Inventors: Chris G. Martin, Manny Kin F. Ma
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Patent number: 6461967Abstract: Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the material on a semiconductor substrate. The material, which has uniform stress therein, is then masked, and the stress in a portion of the material is reduced, such as by implanting ions into an unmasked portion. The mask is removed, and the high stress masked portion of the material is selectively removed, preferably by an etching process. The low stress portion of the material remains and forms a shaped structure. One preferred selective etching process uses a basic etchant. The various methods are used to form raised shaped structures, shaped openings, polysilicon plugs, capacitor storage nodes, surround-gate transistors, free-standing walls, interconnect lines, trench capacitors, and trench isolation regions.Type: GrantFiled: July 16, 2001Date of Patent: October 8, 2002Assignee: Micron Technology, Inc.Inventors: Zhiqiang Wu, Li Li, Thomas A. Figura, Kunal R. Parekh, Pai-Hung Pan, Alan R. Reinberg, Kin F. Ma
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Patent number: 6442101Abstract: A DRAM memory array is disclosed that uses a current limiting circuit employing current feedback to clamp the current flow to reduced levels than were previously possible. The current limiting circuit comprises a long length, depletion mode transistor that has its gate voltage reduced when row-to-column shorts exist to limit the bleed current. An alternative embodiment uses a P-channel FET in series with the depletion mode transistor and has its gate tied to a negative supply and passes current until both digit lines approach approximately 0.3 Volts.Type: GrantFiled: April 12, 2001Date of Patent: August 27, 2002Assignee: Micron Technology, Inc.Inventors: Manny Kin F. Ma, Brian Shirley